target/arm: Handle banking in negative-execution-priority check in cpu_mmu_index()
Now that we have a banked FAULTMASK register and banked exceptions, we can implement the correct check in cpu_mmu_index() for whether the MPU_CTRL.HFNMIENA bit's effect should apply. This bit causes handlers which have requested a negative execution priority to run with the MPU disabled. In v8M the test has to check this for the current security state and so takes account of banking. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 1505240046-11454-17-git-send-email-peter.maydell@linaro.org
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@ -368,6 +368,35 @@ static inline int nvic_exec_prio(NVICState *s)
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return MIN(running, s->exception_prio);
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}
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bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure)
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{
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/* Return true if the requested execution priority is negative
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* for the specified security state, ie that security state
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* has an active NMI or HardFault or has set its FAULTMASK.
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* Note that this is not the same as whether the execution
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* priority is actually negative (for instance AIRCR.PRIS may
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* mean we don't allow FAULTMASK_NS to actually make the execution
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* priority negative). Compare pseudocode IsReqExcPriNeg().
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*/
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NVICState *s = opaque;
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if (s->cpu->env.v7m.faultmask[secure]) {
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return true;
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}
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if (secure ? s->sec_vectors[ARMV7M_EXCP_HARD].active :
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s->vectors[ARMV7M_EXCP_HARD].active) {
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return true;
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}
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if (s->vectors[ARMV7M_EXCP_NMI].active &&
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exc_targets_secure(s, ARMV7M_EXCP_NMI) == secure) {
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return true;
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}
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return false;
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}
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bool armv7m_nvic_can_take_pending_exception(void *opaque)
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{
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NVICState *s = opaque;
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@ -1498,6 +1498,21 @@ int armv7m_nvic_complete_irq(void *opaque, int irq);
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* (v8M ARM ARM I_PKLD.)
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*/
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int armv7m_nvic_raw_execution_priority(void *opaque);
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/**
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* armv7m_nvic_neg_prio_requested: return true if the requested execution
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* priority is negative for the specified security state.
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* @opaque: the NVIC
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* @secure: the security state to test
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* This corresponds to the pseudocode IsReqExecPriNeg().
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*/
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#ifndef CONFIG_USER_ONLY
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bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure);
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#else
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static inline bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure)
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{
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return false;
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}
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#endif
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/* Interface for defining coprocessor registers.
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* Registers are defined in tables of arm_cp_reginfo structs
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@ -2283,11 +2298,7 @@ static inline int cpu_mmu_index(CPUARMState *env, bool ifetch)
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if (arm_feature(env, ARM_FEATURE_M)) {
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ARMMMUIdx mmu_idx = el == 0 ? ARMMMUIdx_MUser : ARMMMUIdx_MPriv;
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/* Execution priority is negative if FAULTMASK is set or
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* we're in a HardFault or NMI handler.
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*/
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if ((env->v7m.exception > 0 && env->v7m.exception <= 3)
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|| env->v7m.faultmask[env->v7m.secure]) {
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if (armv7m_nvic_neg_prio_requested(env->nvic, env->v7m.secure)) {
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mmu_idx = ARMMMUIdx_MNegPri;
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}
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