target/arm: Reuse aa64_va_parameters for setting tbflags
The arm_regime_tbi{0,1} functions are replacable with the new function by giving the lowest and highest address. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190108223129.5570-24-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@ -3015,41 +3015,6 @@ static inline bool arm_cpu_bswap_data(CPUARMState *env)
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}
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#endif
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#ifndef CONFIG_USER_ONLY
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/**
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* arm_regime_tbi0:
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* @env: CPUARMState
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* @mmu_idx: MMU index indicating required translation regime
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*
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* Extracts the TBI0 value from the appropriate TCR for the current EL
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*
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* Returns: the TBI0 value.
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*/
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uint32_t arm_regime_tbi0(CPUARMState *env, ARMMMUIdx mmu_idx);
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/**
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* arm_regime_tbi1:
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* @env: CPUARMState
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* @mmu_idx: MMU index indicating required translation regime
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*
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* Extracts the TBI1 value from the appropriate TCR for the current EL
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*
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* Returns: the TBI1 value.
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*/
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uint32_t arm_regime_tbi1(CPUARMState *env, ARMMMUIdx mmu_idx);
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#else
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/* We can't handle tagged addresses properly in user-only mode */
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static inline uint32_t arm_regime_tbi0(CPUARMState *env, ARMMMUIdx mmu_idx)
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{
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return 0;
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}
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static inline uint32_t arm_regime_tbi1(CPUARMState *env, ARMMMUIdx mmu_idx)
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{
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return 0;
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}
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#endif
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void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,
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target_ulong *cs_base, uint32_t *flags);
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@ -8957,48 +8957,6 @@ static inline ARMMMUIdx stage_1_mmu_idx(ARMMMUIdx mmu_idx)
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return mmu_idx;
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}
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/* Returns TBI0 value for current regime el */
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uint32_t arm_regime_tbi0(CPUARMState *env, ARMMMUIdx mmu_idx)
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{
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TCR *tcr;
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uint32_t el;
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/* For EL0 and EL1, TBI is controlled by stage 1's TCR, so convert
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* a stage 1+2 mmu index into the appropriate stage 1 mmu index.
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*/
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mmu_idx = stage_1_mmu_idx(mmu_idx);
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tcr = regime_tcr(env, mmu_idx);
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el = regime_el(env, mmu_idx);
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if (el > 1) {
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return extract64(tcr->raw_tcr, 20, 1);
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} else {
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return extract64(tcr->raw_tcr, 37, 1);
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}
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}
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/* Returns TBI1 value for current regime el */
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uint32_t arm_regime_tbi1(CPUARMState *env, ARMMMUIdx mmu_idx)
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{
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TCR *tcr;
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uint32_t el;
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/* For EL0 and EL1, TBI is controlled by stage 1's TCR, so convert
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* a stage 1+2 mmu index into the appropriate stage 1 mmu index.
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*/
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mmu_idx = stage_1_mmu_idx(mmu_idx);
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tcr = regime_tcr(env, mmu_idx);
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el = regime_el(env, mmu_idx);
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if (el > 1) {
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return 0;
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} else {
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return extract64(tcr->raw_tcr, 38, 1);
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}
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}
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/* Return the TTBR associated with this translation regime */
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static inline uint64_t regime_ttbr(CPUARMState *env, ARMMMUIdx mmu_idx,
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int ttbrn)
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@ -13054,10 +13012,30 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,
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*pc = env->pc;
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flags = FIELD_DP32(flags, TBFLAG_ANY, AARCH64_STATE, 1);
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/* Get control bits for tagged addresses */
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flags = FIELD_DP32(flags, TBFLAG_A64, TBII,
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(arm_regime_tbi1(env, mmu_idx) << 1) |
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arm_regime_tbi0(env, mmu_idx));
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#ifndef CONFIG_USER_ONLY
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/*
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* Get control bits for tagged addresses. Note that the
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* translator only uses this for instruction addresses.
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*/
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{
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ARMMMUIdx stage1 = stage_1_mmu_idx(mmu_idx);
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ARMVAParameters p0 = aa64_va_parameters_both(env, 0, stage1);
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int tbii, tbid;
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/* FIXME: ARMv8.1-VHE S2 translation regime. */
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if (regime_el(env, stage1) < 2) {
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ARMVAParameters p1 = aa64_va_parameters_both(env, -1, stage1);
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tbid = (p1.tbi << 1) | p0.tbi;
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tbii = tbid & ~((p1.tbid << 1) | p0.tbid);
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} else {
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tbid = p0.tbi;
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tbii = tbid & !p0.tbid;
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}
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flags = FIELD_DP32(flags, TBFLAG_A64, TBII, tbii);
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}
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#endif
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if (cpu_isar_feature(aa64_sve, cpu)) {
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int sve_el = sve_exception_el(env, current_el);
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