x86 queue, 2020-09-18
Cleanups: * Correct the meaning of '0xffffffff' value for hv-spinlocks (Vitaly Kuznetsov) * vmport: Drop superfluous parenthesis (Philippe Mathieu-Daudé) Fixes: * Use generic APIC ID encoding code for EPYC (Babu Moger) -----BEGIN PGP SIGNATURE----- iQJIBAABCAAyFiEEWjIv1avE09usz9GqKAeTb5hNxaYFAl9lGBEUHGVoYWJrb3N0 QHJlZGhhdC5jb20ACgkQKAeTb5hNxaa1ZA//ZdHTcuRwGiXnu6EA/ZUQcWqVUhcB MnbOyBsvUtBtxV/e+CkBRWJ4lGgL8AhCFFeTaayrozD4V9Rdrz8OmThgnMwLHC8v Iw2dcq0xCDEyO/FsAimPE+Xo5FBynzB8u2qPfdpSKXyn8q4l63gqdPbm3ia2BTkL Jh0FcBBrGkfgY60MDFyko7IgpIvWFhhtQihaRjr+PkHD2bil4P5Fw6d7Bq9GqQT0 BYEhyIWgHoJx9pGSugxId9+26bVzDcRI+h0FzcrPeDFDesKFwzdpx8z0bCozjAWQ PUCbeP9J7VGqq2lXhDleaEle4lA+e042ZnkcTbOqfgFsiX2TmzeWdXSPNsE1k/zB 10z1qGeLO5FXqUN9YIZvIc+/S2VsKysWqog8uc+7x97FGEWPFUx7B/nMzk8e95b3 eD6LNAoTPgxS10jji0BmEoGdx/UxDuxYulOrZYKLf5yW1ZWIHiFRO8Q+U9vVOd4H rLKhDMm9qSKTszVkCikrbw3b0X+CPHsBiVvpnnK9TTbr69jGEAfjIC9iJtP6oR+c 735GUqXdO7ldbjuBlu3EUcZjsIafF5dZ53jbNeqoRmU4aHMSy+CE1K4iPfwwsZkP dklCqM+M8hNbkc2HY/x11/JBz21NC0ix51JTAhRmBCpH58ktJ5IhQgfEZHlYf6qE sxIDxeRggXFOLrQ= =TEux -----END PGP SIGNATURE----- Merge remote-tracking branch 'remotes/ehabkost/tags/x86-next-pull-request' into staging x86 queue, 2020-09-18 Cleanups: * Correct the meaning of '0xffffffff' value for hv-spinlocks (Vitaly Kuznetsov) * vmport: Drop superfluous parenthesis (Philippe Mathieu-Daudé) Fixes: * Use generic APIC ID encoding code for EPYC (Babu Moger) # gpg: Signature made Fri 18 Sep 2020 21:26:57 BST # gpg: using RSA key 5A322FD5ABC4D3DBACCFD1AA2807936F984DC5A6 # gpg: issuer "ehabkost@redhat.com" # gpg: Good signature from "Eduardo Habkost <ehabkost@redhat.com>" [full] # Primary key fingerprint: 5A32 2FD5 ABC4 D3DB ACCF D1AA 2807 936F 984D C5A6 * remotes/ehabkost/tags/x86-next-pull-request: i386: Simplify CPUID_8000_001E for AMD i386: Simplify CPUID_8000_001d for AMD hw/i386/vmport: Drop superfluous parenthesis around function typedef i386/kvm: correct the meaning of '0xffffffff' value for hv-spinlocks Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
commit
5df6c87e80
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@ -49,7 +49,7 @@ more efficiently. In particular, this enlightenment allows paravirtualized
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======================
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Enables paravirtualized spinlocks. The parameter indicates how many times
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spinlock acquisition should be attempted before indicating the situation to the
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hypervisor. A special value 0xffffffff indicates "never to retry".
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hypervisor. A special value 0xffffffff indicates "never notify".
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3.4. hv-vpindex
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================
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@ -4,7 +4,7 @@
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#include "hw/isa/isa.h"
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#define TYPE_VMPORT "vmport"
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typedef uint32_t (VMPortReadFunc)(void *opaque, uint32_t address);
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typedef uint32_t VMPortReadFunc(void *opaque, uint32_t address);
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typedef enum {
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VMPORT_CMD_GETVERSION = 10,
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@ -338,68 +338,13 @@ static void encode_cache_cpuid80000006(CPUCacheInfo *l2,
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}
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}
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/*
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* Definitions used for building CPUID Leaf 0x8000001D and 0x8000001E
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* Please refer to the AMD64 Architecture Programmer’s Manual Volume 3.
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* Define the constants to build the cpu topology. Right now, TOPOEXT
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* feature is enabled only on EPYC. So, these constants are based on
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* EPYC supported configurations. We may need to handle the cases if
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* these values change in future.
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*/
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/* Maximum core complexes in a node */
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#define MAX_CCX 2
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/* Maximum cores in a core complex */
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#define MAX_CORES_IN_CCX 4
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/* Maximum cores in a node */
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#define MAX_CORES_IN_NODE 8
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/* Maximum nodes in a socket */
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#define MAX_NODES_PER_SOCKET 4
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/*
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* Figure out the number of nodes required to build this config.
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* Max cores in a node is 8
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*/
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static int nodes_in_socket(int nr_cores)
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{
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int nodes;
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nodes = DIV_ROUND_UP(nr_cores, MAX_CORES_IN_NODE);
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/* Hardware does not support config with 3 nodes, return 4 in that case */
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return (nodes == 3) ? 4 : nodes;
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}
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/*
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* Decide the number of cores in a core complex with the given nr_cores using
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* following set constants MAX_CCX, MAX_CORES_IN_CCX, MAX_CORES_IN_NODE and
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* MAX_NODES_PER_SOCKET. Maintain symmetry as much as possible
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* L3 cache is shared across all cores in a core complex. So, this will also
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* tell us how many cores are sharing the L3 cache.
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*/
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static int cores_in_core_complex(int nr_cores)
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{
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int nodes;
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/* Check if we can fit all the cores in one core complex */
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if (nr_cores <= MAX_CORES_IN_CCX) {
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return nr_cores;
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}
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/* Get the number of nodes required to build this config */
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nodes = nodes_in_socket(nr_cores);
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/*
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* Divide the cores accros all the core complexes
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* Return rounded up value
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*/
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return DIV_ROUND_UP(nr_cores, nodes * MAX_CCX);
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}
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/* Encode cache info for CPUID[8000001D] */
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static void encode_cache_cpuid8000001d(CPUCacheInfo *cache, CPUState *cs,
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uint32_t *eax, uint32_t *ebx,
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uint32_t *ecx, uint32_t *edx)
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static void encode_cache_cpuid8000001d(CPUCacheInfo *cache,
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X86CPUTopoInfo *topo_info,
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uint32_t *eax, uint32_t *ebx,
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uint32_t *ecx, uint32_t *edx)
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{
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uint32_t l3_cores;
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uint32_t l3_threads;
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assert(cache->size == cache->line_size * cache->associativity *
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cache->partitions * cache->sets);
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/* L3 is shared among multiple cores */
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if (cache->level == 3) {
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l3_cores = cores_in_core_complex(cs->nr_cores);
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*eax |= ((l3_cores * cs->nr_threads) - 1) << 14;
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l3_threads = topo_info->cores_per_die * topo_info->threads_per_core;
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*eax |= (l3_threads - 1) << 14;
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} else {
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*eax |= ((cs->nr_threads - 1) << 14);
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*eax |= ((topo_info->threads_per_core - 1) << 14);
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}
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assert(cache->line_size > 0);
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(cache->complex_indexing ? CACHE_COMPLEX_IDX : 0);
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}
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/* Data structure to hold the configuration info for a given core index */
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struct core_topology {
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/* core complex id of the current core index */
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int ccx_id;
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/*
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* Adjusted core index for this core in the topology
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* This can be 0,1,2,3 with max 4 cores in a core complex
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*/
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int core_id;
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/* Node id for this core index */
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int node_id;
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/* Number of nodes in this config */
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int num_nodes;
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};
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/*
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* Build the configuration closely match the EPYC hardware. Using the EPYC
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* hardware configuration values (MAX_CCX, MAX_CORES_IN_CCX, MAX_CORES_IN_NODE)
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* right now. This could change in future.
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* nr_cores : Total number of cores in the config
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* core_id : Core index of the current CPU
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* topo : Data structure to hold all the config info for this core index
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*/
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static void build_core_topology(int nr_cores, int core_id,
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struct core_topology *topo)
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{
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int nodes, cores_in_ccx;
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/* First get the number of nodes required */
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nodes = nodes_in_socket(nr_cores);
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cores_in_ccx = cores_in_core_complex(nr_cores);
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topo->node_id = core_id / (cores_in_ccx * MAX_CCX);
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topo->ccx_id = (core_id % (cores_in_ccx * MAX_CCX)) / cores_in_ccx;
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topo->core_id = core_id % cores_in_ccx;
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topo->num_nodes = nodes;
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}
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/* Encode cache info for CPUID[8000001E] */
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static void encode_topo_cpuid8000001e(CPUState *cs, X86CPU *cpu,
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uint32_t *eax, uint32_t *ebx,
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uint32_t *ecx, uint32_t *edx)
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static void encode_topo_cpuid8000001e(X86CPU *cpu, X86CPUTopoInfo *topo_info,
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uint32_t *eax, uint32_t *ebx,
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uint32_t *ecx, uint32_t *edx)
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{
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struct core_topology topo = {0};
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unsigned long nodes;
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int shift;
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X86CPUTopoIDs topo_ids;
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x86_topo_ids_from_apicid(cpu->apic_id, topo_info, &topo_ids);
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build_core_topology(cs->nr_cores, cpu->core_id, &topo);
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*eax = cpu->apic_id;
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/*
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* CPUID_Fn8000001E_EBX
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* 31:16 Reserved
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* 15:8 Threads per core (The number of threads per core is
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* Threads per core + 1)
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* 7:0 Core id (see bit decoding below)
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* SMT:
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* 4:3 node id
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* 2 Core complex id
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* 1:0 Core id
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* Non SMT:
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* 5:4 node id
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* 3 Core complex id
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* 1:0 Core id
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* CPUID_Fn8000001E_EBX [Core Identifiers] (CoreId)
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* Read-only. Reset: 0000_XXXXh.
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* See Core::X86::Cpuid::ExtApicId.
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* Core::X86::Cpuid::CoreId_lthree[1:0]_core[3:0]_thread[1:0];
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* Bits Description
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* 31:16 Reserved.
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* 15:8 ThreadsPerCore: threads per core. Read-only. Reset: XXh.
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* The number of threads per core is ThreadsPerCore+1.
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* 7:0 CoreId: core ID. Read-only. Reset: XXh.
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*
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* NOTE: CoreId is already part of apic_id. Just use it. We can
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* use all the 8 bits to represent the core_id here.
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*/
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if (cs->nr_threads - 1) {
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*ebx = ((cs->nr_threads - 1) << 8) | (topo.node_id << 3) |
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(topo.ccx_id << 2) | topo.core_id;
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} else {
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*ebx = (topo.node_id << 4) | (topo.ccx_id << 3) | topo.core_id;
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}
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*ebx = ((topo_info->threads_per_core - 1) << 8) | (topo_ids.core_id & 0xFF);
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/*
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* CPUID_Fn8000001E_ECX
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* 31:11 Reserved
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* 10:8 Nodes per processor (Nodes per processor is number of nodes + 1)
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* 7:0 Node id (see bit decoding below)
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* 2 Socket id
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* 1:0 Node id
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* CPUID_Fn8000001E_ECX [Node Identifiers] (NodeId)
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* Read-only. Reset: 0000_0XXXh.
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* Core::X86::Cpuid::NodeId_lthree[1:0]_core[3:0]_thread[1:0];
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* Bits Description
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* 31:11 Reserved.
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* 10:8 NodesPerProcessor: Node per processor. Read-only. Reset: XXXb.
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* ValidValues:
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* Value Description
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* 000b 1 node per processor.
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* 001b 2 nodes per processor.
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* 010b Reserved.
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* 011b 4 nodes per processor.
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* 111b-100b Reserved.
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* 7:0 NodeId: Node ID. Read-only. Reset: XXh.
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*
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* NOTE: Hardware reserves 3 bits for number of nodes per processor.
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* But users can create more nodes than the actual hardware can
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* support. To genaralize we can use all the upper 8 bits for nodes.
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* NodeId is combination of node and socket_id which is already decoded
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* in apic_id. Just use it by shifting.
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*/
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if (topo.num_nodes <= 4) {
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*ecx = ((topo.num_nodes - 1) << 8) | (cpu->socket_id << 2) |
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topo.node_id;
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} else {
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/*
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* Node id fix up. Actual hardware supports up to 4 nodes. But with
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* more than 32 cores, we may end up with more than 4 nodes.
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* Node id is a combination of socket id and node id. Only requirement
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* here is that this number should be unique accross the system.
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* Shift the socket id to accommodate more nodes. We dont expect both
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* socket id and node id to be big number at the same time. This is not
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* an ideal config but we need to to support it. Max nodes we can have
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* is 32 (255/8) with 8 cores per node and 255 max cores. We only need
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* 5 bits for nodes. Find the left most set bit to represent the total
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* number of nodes. find_last_bit returns last set bit(0 based). Left
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* shift(+1) the socket id to represent all the nodes.
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*/
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nodes = topo.num_nodes - 1;
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shift = find_last_bit(&nodes, 8);
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*ecx = ((topo.num_nodes - 1) << 8) | (cpu->socket_id << (shift + 1)) |
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topo.node_id;
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}
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*ecx = ((topo_info->dies_per_pkg - 1) << 8) |
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((cpu->apic_id >> apicid_die_offset(topo_info)) & 0xFF);
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*edx = 0;
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}
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@ -5995,20 +5891,20 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
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}
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switch (count) {
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case 0: /* L1 dcache info */
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encode_cache_cpuid8000001d(env->cache_info_amd.l1d_cache, cs,
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eax, ebx, ecx, edx);
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encode_cache_cpuid8000001d(env->cache_info_amd.l1d_cache,
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&topo_info, eax, ebx, ecx, edx);
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break;
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case 1: /* L1 icache info */
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encode_cache_cpuid8000001d(env->cache_info_amd.l1i_cache, cs,
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eax, ebx, ecx, edx);
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encode_cache_cpuid8000001d(env->cache_info_amd.l1i_cache,
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&topo_info, eax, ebx, ecx, edx);
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break;
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case 2: /* L2 cache info */
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encode_cache_cpuid8000001d(env->cache_info_amd.l2_cache, cs,
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eax, ebx, ecx, edx);
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encode_cache_cpuid8000001d(env->cache_info_amd.l2_cache,
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&topo_info, eax, ebx, ecx, edx);
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break;
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case 3: /* L3 cache info */
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encode_cache_cpuid8000001d(env->cache_info_amd.l3_cache, cs,
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eax, ebx, ecx, edx);
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encode_cache_cpuid8000001d(env->cache_info_amd.l3_cache,
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&topo_info, eax, ebx, ecx, edx);
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break;
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default: /* end of info */
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*eax = *ebx = *ecx = *edx = 0;
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@ -6017,7 +5913,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
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break;
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case 0x8000001E:
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assert(cpu->core_id <= 255);
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encode_topo_cpuid8000001e(cs, cpu,
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encode_topo_cpuid8000001e(cpu, &topo_info,
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eax, ebx, ecx, edx);
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break;
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case 0xC0000000:
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|
@ -7263,7 +7159,7 @@ static Property x86_cpu_properties[] = {
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DEFINE_PROP_BOOL("pmu", X86CPU, enable_pmu, false),
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DEFINE_PROP_UINT32("hv-spinlocks", X86CPU, hyperv_spinlock_attempts,
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HYPERV_SPINLOCK_NEVER_RETRY),
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HYPERV_SPINLOCK_NEVER_NOTIFY),
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DEFINE_PROP_BIT64("hv-relaxed", X86CPU, hyperv_features,
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HYPERV_FEAT_RELAXED, 0),
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DEFINE_PROP_BIT64("hv-vapic", X86CPU, hyperv_features,
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|
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|
@ -991,8 +991,8 @@ typedef uint64_t FeatureWordArray[FEATURE_WORDS];
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#define HYPERV_FEAT_IPI 13
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#define HYPERV_FEAT_STIMER_DIRECT 14
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#ifndef HYPERV_SPINLOCK_NEVER_RETRY
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#define HYPERV_SPINLOCK_NEVER_RETRY 0xFFFFFFFF
|
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#ifndef HYPERV_SPINLOCK_NEVER_NOTIFY
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#define HYPERV_SPINLOCK_NEVER_NOTIFY 0xFFFFFFFF
|
||||
#endif
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#define EXCP00_DIVZ 0
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|
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|
@ -730,7 +730,7 @@ static bool hyperv_enabled(X86CPU *cpu)
|
|||
{
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||||
CPUState *cs = CPU(cpu);
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||||
return kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV) > 0 &&
|
||||
((cpu->hyperv_spinlock_attempts != HYPERV_SPINLOCK_NEVER_RETRY) ||
|
||||
((cpu->hyperv_spinlock_attempts != HYPERV_SPINLOCK_NEVER_NOTIFY) ||
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||||
cpu->hyperv_features || cpu->hyperv_passthrough);
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}
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||||
|
@ -1236,7 +1236,7 @@ static int hyperv_handle_properties(CPUState *cs,
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|||
env->features[FEAT_HV_RECOMM_EAX] = c->eax;
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||||
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||||
/* hv-spinlocks may have been overriden */
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||||
if (cpu->hyperv_spinlock_attempts != HYPERV_SPINLOCK_NEVER_RETRY) {
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||||
if (cpu->hyperv_spinlock_attempts != HYPERV_SPINLOCK_NEVER_NOTIFY) {
|
||||
c->ebx = cpu->hyperv_spinlock_attempts;
|
||||
}
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||||
}
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||||
|
|
Loading…
Reference in a new issue