target-xtensa: implement depbits instruction
This option provides an instruction for depositing a bit field from the least significant position of one register to an arbitrary position in another register. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
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@ -64,6 +64,7 @@ enum {
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XTENSA_OPTION_MP_SYNCHRO,
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XTENSA_OPTION_MP_SYNCHRO,
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XTENSA_OPTION_CONDITIONAL_STORE,
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XTENSA_OPTION_CONDITIONAL_STORE,
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XTENSA_OPTION_ATOMCTL,
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XTENSA_OPTION_ATOMCTL,
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XTENSA_OPTION_DEPBITS,
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/* Interrupts and exceptions */
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/* Interrupts and exceptions */
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XTENSA_OPTION_EXCEPTION,
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XTENSA_OPTION_EXCEPTION,
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@ -30,6 +30,10 @@
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{ .targno = (no), .type = (typ), .group = (grp), .size = (sz) },
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{ .targno = (no), .type = (typ), .group = (grp), .size = (sz) },
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#define XTREG_END { .targno = -1 },
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#define XTREG_END { .targno = -1 },
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#ifndef XCHAL_HAVE_DEPBITS
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#define XCHAL_HAVE_DEPBITS 0
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#endif
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#ifndef XCHAL_HAVE_DIV32
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#ifndef XCHAL_HAVE_DIV32
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#define XCHAL_HAVE_DIV32 0
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#define XCHAL_HAVE_DIV32 0
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#endif
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#endif
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@ -69,6 +73,7 @@
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XCHAL_OPTION(XCHAL_HAVE_S32C1I, XTENSA_OPTION_CONDITIONAL_STORE) | \
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XCHAL_OPTION(XCHAL_HAVE_S32C1I, XTENSA_OPTION_CONDITIONAL_STORE) | \
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XCHAL_OPTION(XCHAL_HAVE_S32C1I && XCHAL_HW_MIN_VERSION >= 230000, \
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XCHAL_OPTION(XCHAL_HAVE_S32C1I && XCHAL_HW_MIN_VERSION >= 230000, \
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XTENSA_OPTION_ATOMCTL) | \
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XTENSA_OPTION_ATOMCTL) | \
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XCHAL_OPTION(XCHAL_HAVE_DEPBITS, XTENSA_OPTION_DEPBITS) | \
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/* Interrupts and exceptions */ \
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/* Interrupts and exceptions */ \
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XCHAL_OPTION(XCHAL_HAVE_EXCEPTIONS, XTENSA_OPTION_EXCEPTION) | \
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XCHAL_OPTION(XCHAL_HAVE_EXCEPTIONS, XTENSA_OPTION_EXCEPTION) | \
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XCHAL_OPTION(XCHAL_HAVE_VECBASE, XTENSA_OPTION_RELOCATABLE_VECTOR) | \
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XCHAL_OPTION(XCHAL_HAVE_VECBASE, XTENSA_OPTION_RELOCATABLE_VECTOR) | \
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@ -1972,6 +1972,16 @@ static void disas_xtensa_insn(CPUXtensaState *env, DisasContext *dc)
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break;
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break;
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case 10: /*FP0*/
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case 10: /*FP0*/
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/*DEPBITS*/
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if (option_enabled(dc, XTENSA_OPTION_DEPBITS)) {
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if (!gen_window_check2(dc, RRR_S, RRR_T)) {
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break;
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}
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tcg_gen_deposit_i32(cpu_R[RRR_T], cpu_R[RRR_T], cpu_R[RRR_S],
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OP2, RRR_R + 1);
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break;
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}
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HAS_OPTION(XTENSA_OPTION_FP_COPROCESSOR);
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HAS_OPTION(XTENSA_OPTION_FP_COPROCESSOR);
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switch (OP2) {
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switch (OP2) {
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case 0: /*ADD.Sf*/
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case 0: /*ADD.Sf*/
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@ -2106,6 +2116,16 @@ static void disas_xtensa_insn(CPUXtensaState *env, DisasContext *dc)
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break;
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break;
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case 11: /*FP1*/
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case 11: /*FP1*/
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/*DEPBITS*/
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if (option_enabled(dc, XTENSA_OPTION_DEPBITS)) {
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if (!gen_window_check2(dc, RRR_S, RRR_T)) {
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break;
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}
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tcg_gen_deposit_i32(cpu_R[RRR_T], cpu_R[RRR_T], cpu_R[RRR_S],
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OP2 + 16, RRR_R + 1);
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break;
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}
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HAS_OPTION(XTENSA_OPTION_FP_COPROCESSOR);
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HAS_OPTION(XTENSA_OPTION_FP_COPROCESSOR);
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#define gen_compare(rel, br, a, b) \
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#define gen_compare(rel, br, a, b) \
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