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target/mips/mips-defs: Rename ISA_MIPS32R5 as ISA_MIPS_R5

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The MIPS ISA release 5 is common to 32/64-bit CPUs.

To avoid holes in the insn_flags type, update the
definition with the next available bit.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20210104221154.3127610-15-f4bug@amsat.org>
This commit is contained in:
Philippe Mathieu-Daudé 2020-12-16 12:30:11 +01:00
parent bae4b15aa4
commit 5f89ce4fc2
2 changed files with 3 additions and 3 deletions
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4
target/mips/mips-defs.h
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@ -19,7 +19,7 @@
#define ISA_MIPS_R1 0x0000000000000020ULL
#define ISA_MIPS_R2 0x0000000000000040ULL
#define ISA_MIPS_R3 0x0000000000000080ULL
#define ISA_MIPS32R5 0x0000000000000800ULL
#define ISA_MIPS_R5 0x0000000000000100ULL
#define ISA_MIPS32R6 0x0000000000002000ULL
#define ISA_NANOMIPS32 0x0000000000008000ULL
/*
@ -81,7 +81,7 @@
#define CPU_MIPS64R3 (CPU_MIPS64R2 | CPU_MIPS32R3)
/* MIPS Technologies "Release 5" */
#define CPU_MIPS32R5 (CPU_MIPS32R3 | ISA_MIPS32R5)
#define CPU_MIPS32R5 (CPU_MIPS32R3 | ISA_MIPS_R5)
#define CPU_MIPS64R5 (CPU_MIPS64R3 | CPU_MIPS32R5)
/* MIPS Technologies "Release 6" */

2
target/mips/translate.c
View file

@ -10993,7 +10993,7 @@ static void gen_cp0(CPUMIPSState *env, DisasContext *ctx, uint32_t opc,
if (ctx->opcode & (1 << bit_shift)) {
/* OPC_ERETNC */
opn = "eretnc";
check_insn(ctx, ISA_MIPS32R5);
check_insn(ctx, ISA_MIPS_R5);
gen_helper_eretnc(cpu_env);
} else {
/* OPC_ERET */