target-xtensa: provide HW confg ID registers
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
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676056d4f1
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@ -59,6 +59,8 @@ static void xtensa_cpu_reset(CPUState *s)
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env->sregs[CACHEATTR] = 0x22222222;
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env->sregs[CACHEATTR] = 0x22222222;
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env->sregs[ATOMCTL] = xtensa_option_enabled(env->config,
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env->sregs[ATOMCTL] = xtensa_option_enabled(env->config,
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XTENSA_OPTION_ATOMCTL) ? 0x28 : 0x15;
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XTENSA_OPTION_ATOMCTL) ? 0x28 : 0x15;
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env->sregs[CONFIGID0] = env->config->configid[0];
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env->sregs[CONFIGID1] = env->config->configid[1];
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env->pending_irq_level = 0;
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env->pending_irq_level = 0;
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reset_mmu(env);
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reset_mmu(env);
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@ -135,9 +135,11 @@ enum {
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IBREAKA = 128,
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IBREAKA = 128,
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DBREAKA = 144,
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DBREAKA = 144,
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DBREAKC = 160,
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DBREAKC = 160,
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CONFIGID0 = 176,
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EPC1 = 177,
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EPC1 = 177,
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DEPC = 192,
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DEPC = 192,
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EPS2 = 194,
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EPS2 = 194,
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CONFIGID1 = 208,
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EXCSAVE1 = 209,
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EXCSAVE1 = 209,
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CPENABLE = 224,
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CPENABLE = 224,
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INTSET = 226,
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INTSET = 226,
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@ -321,6 +323,8 @@ typedef struct XtensaConfig {
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unsigned nibreak;
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unsigned nibreak;
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unsigned ndbreak;
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unsigned ndbreak;
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uint32_t configid[2];
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uint32_t clock_freq_khz;
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uint32_t clock_freq_khz;
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xtensa_tlb itlb;
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xtensa_tlb itlb;
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@ -319,6 +319,12 @@
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.nibreak = XCHAL_NUM_IBREAK, \
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.nibreak = XCHAL_NUM_IBREAK, \
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.ndbreak = XCHAL_NUM_DBREAK
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.ndbreak = XCHAL_NUM_DBREAK
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#define CONFIG_SECTION \
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.configid = { \
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XCHAL_HW_CONFIGID0, \
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XCHAL_HW_CONFIGID1, \
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}
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#define DEFAULT_SECTIONS \
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#define DEFAULT_SECTIONS \
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.options = XTENSA_OPTIONS, \
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.options = XTENSA_OPTIONS, \
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.nareg = XCHAL_NUM_AREGS, \
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.nareg = XCHAL_NUM_AREGS, \
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@ -326,7 +332,8 @@
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EXCEPTIONS_SECTION, \
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EXCEPTIONS_SECTION, \
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INTERRUPTS_SECTION, \
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INTERRUPTS_SECTION, \
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TLB_SECTION, \
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TLB_SECTION, \
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DEBUG_SECTION
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DEBUG_SECTION, \
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CONFIG_SECTION
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#if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI + 1 <= 2
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#if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI + 1 <= 2
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@ -98,12 +98,15 @@ typedef struct XtensaReg {
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#define XTENSA_REG(regname, opt) XTENSA_REG_ACCESS(regname, opt, SR_RWX)
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#define XTENSA_REG(regname, opt) XTENSA_REG_ACCESS(regname, opt, SR_RWX)
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#define XTENSA_REG_BITS(regname, opt) { \
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#define XTENSA_REG_BITS_ACCESS(regname, opt, acc) { \
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.name = (regname), \
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.name = (regname), \
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.opt_bits = (opt), \
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.opt_bits = (opt), \
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.access = SR_RWX, \
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.access = (acc), \
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}
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}
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#define XTENSA_REG_BITS(regname, opt) \
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XTENSA_REG_BITS_ACCESS(regname, opt, SR_RWX)
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static const XtensaReg sregnames[256] = {
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static const XtensaReg sregnames[256] = {
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[LBEG] = XTENSA_REG("LBEG", XTENSA_OPTION_LOOP),
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[LBEG] = XTENSA_REG("LBEG", XTENSA_OPTION_LOOP),
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[LEND] = XTENSA_REG("LEND", XTENSA_OPTION_LOOP),
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[LEND] = XTENSA_REG("LEND", XTENSA_OPTION_LOOP),
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@ -134,6 +137,7 @@ static const XtensaReg sregnames[256] = {
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[DBREAKA + 1] = XTENSA_REG("DBREAKA1", XTENSA_OPTION_DEBUG),
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[DBREAKA + 1] = XTENSA_REG("DBREAKA1", XTENSA_OPTION_DEBUG),
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[DBREAKC] = XTENSA_REG("DBREAKC0", XTENSA_OPTION_DEBUG),
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[DBREAKC] = XTENSA_REG("DBREAKC0", XTENSA_OPTION_DEBUG),
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[DBREAKC + 1] = XTENSA_REG("DBREAKC1", XTENSA_OPTION_DEBUG),
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[DBREAKC + 1] = XTENSA_REG("DBREAKC1", XTENSA_OPTION_DEBUG),
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[CONFIGID0] = XTENSA_REG_BITS_ACCESS("CONFIGID0", XTENSA_OPTION_ALL, SR_R),
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[EPC1] = XTENSA_REG("EPC1", XTENSA_OPTION_EXCEPTION),
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[EPC1] = XTENSA_REG("EPC1", XTENSA_OPTION_EXCEPTION),
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[EPC1 + 1] = XTENSA_REG("EPC2", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
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[EPC1 + 1] = XTENSA_REG("EPC2", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
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[EPC1 + 2] = XTENSA_REG("EPC3", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
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[EPC1 + 2] = XTENSA_REG("EPC3", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
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@ -148,6 +152,7 @@ static const XtensaReg sregnames[256] = {
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[EPS2 + 3] = XTENSA_REG("EPS5", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
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[EPS2 + 3] = XTENSA_REG("EPS5", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
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[EPS2 + 4] = XTENSA_REG("EPS6", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
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[EPS2 + 4] = XTENSA_REG("EPS6", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
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[EPS2 + 5] = XTENSA_REG("EPS7", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
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[EPS2 + 5] = XTENSA_REG("EPS7", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
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[CONFIGID1] = XTENSA_REG_BITS_ACCESS("CONFIGID1", XTENSA_OPTION_ALL, SR_R),
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[EXCSAVE1] = XTENSA_REG("EXCSAVE1", XTENSA_OPTION_EXCEPTION),
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[EXCSAVE1] = XTENSA_REG("EXCSAVE1", XTENSA_OPTION_EXCEPTION),
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[EXCSAVE1 + 1] = XTENSA_REG("EXCSAVE2",
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[EXCSAVE1 + 1] = XTENSA_REG("EXCSAVE2",
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XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
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XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
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