Delegate setup of TCG temporaries to targets

Delegate TCG temp_buf setup to targets, so that they can use a stack
frame later instead.

Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
stable-0.15
Blue Swirl 2011-05-14 12:58:04 +00:00
parent cea5f9a28f
commit 614f104dfd
10 changed files with 18 additions and 2 deletions

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@ -1804,6 +1804,8 @@ static void tcg_target_init(TCGContext *s)
tcg_regset_set_reg(s->reserved_regs, TCG_REG_PC);
tcg_add_target_add_op_defs(arm_op_defs);
tcg_set_frame(s, TCG_AREG0, offsetof(CPUState, temp_buf),
CPU_TEMP_BUF_NLONGS * sizeof(long));
}
static inline void tcg_out_ld(TCGContext *s, TCGType type, int arg,

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@ -1682,4 +1682,6 @@ static void tcg_target_init(TCGContext *s)
tcg_regset_set_reg(s->reserved_regs, TCG_REG_R31); /* ble link reg */
tcg_add_target_add_op_defs(hppa_op_defs);
tcg_set_frame(s, TCG_AREG0, offsetof(CPUState, temp_buf),
CPU_TEMP_BUF_NLONGS * sizeof(long));
}

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@ -1981,4 +1981,6 @@ static void tcg_target_init(TCGContext *s)
tcg_regset_set_reg(s->reserved_regs, TCG_REG_ESP);
tcg_add_target_add_op_defs(x86_op_defs);
tcg_set_frame(s, TCG_AREG0, offsetof(CPUState, temp_buf),
CPU_TEMP_BUF_NLONGS * sizeof(long));
}

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@ -2388,4 +2388,6 @@ static void tcg_target_init(TCGContext *s)
tcg_regset_set_reg(s->reserved_regs, TCG_REG_R6);
tcg_add_target_add_op_defs(ia64_op_defs);
tcg_set_frame(s, TCG_AREG0, offsetof(CPUState, temp_buf),
CPU_TEMP_BUF_NLONGS * sizeof(long));
}

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@ -1528,4 +1528,6 @@ static void tcg_target_init(TCGContext *s)
tcg_regset_set_reg(s->reserved_regs, TCG_REG_SP); /* stack pointer */
tcg_add_target_add_op_defs(mips_op_defs);
tcg_set_frame(s, TCG_AREG0, offsetof(CPUState, temp_buf),
CPU_TEMP_BUF_NLONGS * sizeof(long));
}

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@ -1919,4 +1919,6 @@ static void tcg_target_init(TCGContext *s)
#endif
tcg_add_target_add_op_defs(ppc_op_defs);
tcg_set_frame(s, TCG_AREG0, offsetof(CPUState, temp_buf),
CPU_TEMP_BUF_NLONGS * sizeof(long));
}

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@ -1696,4 +1696,6 @@ static void tcg_target_init (TCGContext *s)
tcg_regset_set_reg (s->reserved_regs, TCG_REG_R13);
tcg_add_target_add_op_defs (ppc_op_defs);
tcg_set_frame(s, TCG_AREG0, offsetof(CPUState, temp_buf),
CPU_TEMP_BUF_NLONGS * sizeof(long));
}

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@ -2291,6 +2291,8 @@ static void tcg_target_init(TCGContext *s)
tcg_regset_set_reg(s->reserved_regs, TCG_REG_CALL_STACK);
tcg_add_target_add_op_defs(s390_op_defs);
tcg_set_frame(s, TCG_AREG0, offsetof(CPUState, temp_buf),
CPU_TEMP_BUF_NLONGS * sizeof(long));
}
static void tcg_target_qemu_prologue(TCGContext *s)

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@ -1566,4 +1566,6 @@ static void tcg_target_init(TCGContext *s)
tcg_regset_set_reg(s->reserved_regs, TCG_REG_O6);
tcg_regset_set_reg(s->reserved_regs, TCG_REG_O7);
tcg_add_target_add_op_defs(sparc_op_defs);
tcg_set_frame(s, TCG_AREG0, offsetof(CPUState, temp_buf),
CPU_TEMP_BUF_NLONGS * sizeof(long));
}

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@ -43,8 +43,6 @@ uint8_t gen_opc_instr_start[OPC_BUF_SIZE];
void cpu_gen_init(void)
{
tcg_context_init(&tcg_ctx);
tcg_set_frame(&tcg_ctx, TCG_AREG0, offsetof(CPUState, temp_buf),
CPU_TEMP_BUF_NLONGS * sizeof(long));
}
/* return non zero if the very first instruction is invalid so that