PPC: 4xx: Qdevify the 440 PCI host controller
Due to popular demand, this qdevifies the PCI host controller of 4xx SoCs the same way as e500. We have to introduce a small stub function for pci init that will be removed in a later patch, once we qdev'ified the board, to keep the build working. Signed-off-by: Alexander Graf <agraf@suse.de>
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acd1bf9083
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623f7c2172
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@ -34,6 +34,15 @@
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static target_phys_addr_t entry;
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static PCIBus *ppc4xx_pci_init(CPUState *env, qemu_irq pci_irqs[4],
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target_phys_addr_t config_space,
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target_phys_addr_t int_ack,
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target_phys_addr_t special_cycle,
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target_phys_addr_t registers)
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{
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return NULL;
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}
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static int bamboo_load_device_tree(target_phys_addr_t addr,
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uint32_t ramsize,
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target_phys_addr_t initrd_base,
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121
hw/ppc4xx_pci.c
121
hw/ppc4xx_pci.c
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@ -49,13 +49,14 @@ struct PCITargetMap {
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#define PPC4xx_PCI_NR_PTMS 2
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struct PPC4xxPCIState {
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PCIHostState pci_state;
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struct PCIMasterMap pmm[PPC4xx_PCI_NR_PMMS];
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struct PCITargetMap ptm[PPC4xx_PCI_NR_PTMS];
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qemu_irq irq[4];
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PCIHostState pci_state;
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PCIDevice *pci_dev;
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MemoryRegion iomem_addr;
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MemoryRegion iomem_regs;
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MemoryRegion container;
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MemoryRegion iomem;
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};
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typedef struct PPC4xxPCIState PPC4xxPCIState;
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@ -83,8 +84,10 @@ typedef struct PPC4xxPCIState PPC4xxPCIState;
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#define PCIL0_PTM1LA 0x34
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#define PCIL0_PTM2MS 0x38
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#define PCIL0_PTM2LA 0x3c
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#define PCI_REG_BASE 0x800000
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#define PCI_REG_SIZE 0x40
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#define PCI_ALL_SIZE (PCI_REG_BASE + PCI_REG_SIZE)
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static uint64_t pci4xx_cfgaddr_read(void *opaque, target_phys_addr_t addr,
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unsigned size)
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@ -314,7 +317,6 @@ static const VMStateDescription vmstate_ppc4xx_pci = {
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.minimum_version_id = 1,
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.minimum_version_id_old = 1,
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.fields = (VMStateField[]) {
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VMSTATE_PCI_DEVICE_POINTER(pci_dev, PPC4xxPCIState),
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VMSTATE_STRUCT_ARRAY(pmm, PPC4xxPCIState, PPC4xx_PCI_NR_PMMS, 1,
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vmstate_pci_master_map,
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struct PCIMasterMap),
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@ -326,60 +328,63 @@ static const VMStateDescription vmstate_ppc4xx_pci = {
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};
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/* XXX Interrupt acknowledge cycles not supported. */
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PCIBus *ppc4xx_pci_init(CPUState *env, qemu_irq pci_irqs[4],
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target_phys_addr_t config_space,
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target_phys_addr_t int_ack,
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target_phys_addr_t special_cycle,
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target_phys_addr_t registers)
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static int ppc4xx_pcihost_initfn(SysBusDevice *dev)
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{
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PPC4xxPCIState *controller;
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static int ppc4xx_pci_id;
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uint8_t *pci_conf;
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PPC4xxPCIState *s;
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PCIHostState *h;
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PCIBus *b;
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int i;
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controller = g_malloc0(sizeof(PPC4xxPCIState));
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h = FROM_SYSBUS(PCIHostState, sysbus_from_qdev(dev));
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s = DO_UPCAST(PPC4xxPCIState, pci_state, h);
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controller->pci_state.bus = pci_register_bus(NULL, "pci",
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ppc4xx_pci_set_irq,
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ppc4xx_pci_map_irq,
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pci_irqs,
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get_system_memory(),
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get_system_io(),
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0, 4);
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controller->pci_dev = pci_register_device(controller->pci_state.bus,
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"host bridge", sizeof(PCIDevice),
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0, NULL, NULL);
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pci_conf = controller->pci_dev->config;
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pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_IBM);
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pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_IBM_440GX);
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pci_config_set_class(pci_conf, PCI_CLASS_BRIDGE_OTHER);
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/* CFGADDR */
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memory_region_init_io(&controller->iomem_addr, &pci4xx_cfgaddr_ops,
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controller, "pci.cfgaddr", 4);
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memory_region_add_subregion(get_system_memory(),
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config_space + PCIC0_CFGADDR,
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&controller->iomem_addr);
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/* CFGDATA */
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memory_region_init_io(&controller->pci_state.data_mem,
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&pci_host_data_be_ops,
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&controller->pci_state, "pci-conf-data", 4);
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memory_region_add_subregion(get_system_memory(),
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config_space + PCIC0_CFGDATA,
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&controller->pci_state.data_mem);
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/* Internal registers */
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memory_region_init_io(&controller->iomem_regs, &pci_reg_ops, controller,
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"pci.regs", PCI_REG_SIZE);
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memory_region_add_subregion(get_system_memory(), registers,
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&controller->iomem_regs);
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qemu_register_reset(ppc4xx_pci_reset, controller);
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/* XXX load/save code not tested. */
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vmstate_register(&controller->pci_dev->qdev, ppc4xx_pci_id++,
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&vmstate_ppc4xx_pci, controller);
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return controller->pci_state.bus;
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for (i = 0; i < ARRAY_SIZE(s->irq); i++) {
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sysbus_init_irq(dev, &s->irq[i]);
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}
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b = pci_register_bus(&s->pci_state.busdev.qdev, NULL, ppc4xx_pci_set_irq,
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ppc4xx_pci_map_irq, s->irq, get_system_memory(),
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get_system_io(), 0, 4);
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s->pci_state.bus = b;
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pci_create_simple(b, 0, "ppc4xx-host-bridge");
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/* XXX split into 2 memory regions, one for config space, one for regs */
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memory_region_init(&s->container, "pci-container", PCI_ALL_SIZE);
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memory_region_init_io(&h->conf_mem, &pci_host_conf_le_ops, h,
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"pci-conf-idx", 4);
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memory_region_init_io(&h->data_mem, &pci_host_data_le_ops, h,
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"pci-conf-data", 4);
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memory_region_init_io(&s->iomem, &pci_reg_ops, s,
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"pci.reg", PCI_REG_SIZE);
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memory_region_add_subregion(&s->container, PCIC0_CFGADDR, &h->conf_mem);
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memory_region_add_subregion(&s->container, PCIC0_CFGDATA, &h->data_mem);
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memory_region_add_subregion(&s->container, PCI_REG_BASE, &s->iomem);
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sysbus_init_mmio(dev, &s->container);
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qemu_register_reset(ppc4xx_pci_reset, s);
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return 0;
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}
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static PCIDeviceInfo ppc4xx_host_bridge_info = {
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.qdev.name = "ppc4xx-host-bridge",
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.qdev.desc = "Host bridge",
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.qdev.size = sizeof(PCIDevice),
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.vendor_id = PCI_VENDOR_ID_IBM,
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.device_id = PCI_DEVICE_ID_IBM_440GX,
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.class_id = PCI_CLASS_BRIDGE_OTHER,
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};
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static SysBusDeviceInfo ppc4xx_pcihost_info = {
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.init = ppc4xx_pcihost_initfn,
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.qdev.name = "ppc4xx-pcihost",
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.qdev.size = sizeof(PPC4xxPCIState),
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.qdev.vmsd = &vmstate_ppc4xx_pci,
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};
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static void ppc4xx_pci_register(void)
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{
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sysbus_register_withprop(&ppc4xx_pcihost_info);
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pci_qdev_register(&ppc4xx_host_bridge_info);
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}
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device_init(ppc4xx_pci_register);
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