-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1 iQIcBAABAgAGBQJVFddzAAoJEH3vgQaq/DkOF4gQAMLRh84LWGntsegTRZGY+Wqq WOzs8xnTlKOS3Ebu6npHo53/PRkGuD9FUDRMOc71+n0IzVjvZ+7CKHSYwmQ4qcMU 1lXsTt5M+ZhxDZFtcAuFfjKPv60CdauPtxfQo+wLZzoWaoEho1HN8oSi4uiL+bP9 P+29FxiOfQJES5qIQTza07RRQTwOqCxG8XwLNmHepu02uJm8BeEmUvQ0J/uvjnNi liUKzYH1lzI4URuCzcW95bR0vnN4dhQ+aWAazPnNgBWe/M1AQnP7ehUODT2y6vul mk5y9iI68xhBX3j9kVBRB7Wdp+X/c6mNAXrKG/Qwph4Mu7NSVfJZZYS2yJ/DXtzu BgT+uvFs7iZWkI/K2XV8hZi3r6NOCIGoBAg4MGfrniabsspwM8PmUdPq7/Zp/+lG jmZZIGv0fi3kSghDVi+6L/2uPa5TXutmhzU9J0rLlYlSXYpJkYCZiU2GsODLqS4g RbNd1FxcFLuEUowxlnrPZ2PTDRaaSp6ZLd67498Sq4YgUdWZwL2dvaWWu9yYAnQ5 GO/OhI3t+fkDVjt4xRzQkmwrXyytahOD7Ddi8QKzjC7z+aVRW5ZtTLlRlYUkUBk6 KLyza3ye8ZJ0rMAtcFT2V/tUzWTHLnRja7Niowoqoxc4D8duuKny/I9NMG6jFoB0 g+64eTw9HidJ2EdwS0F8 =1ygA -----END PGP SIGNATURE----- Merge remote-tracking branch 'remotes/jnsnow/tags/ide-pull-request' into staging # gpg: Signature made Fri Mar 27 22:19:31 2015 GMT using RSA key ID AAFC390E # gpg: Good signature from "John Snow (John Huston) <jsnow@redhat.com>" # gpg: WARNING: This key is not certified with sufficiently trusted signatures! # gpg: It is not certain that the signature belongs to the owner. # Primary key fingerprint: FAEB 9711 A12C F475 812F 18F2 88A9 064D 1835 61EB # Subkey fingerprint: F9B7 ABDB BCAC DF95 BE76 CBD0 7DEF 8106 AAFC 390E * remotes/jnsnow/tags/ide-pull-request: AHCI: Protect cmd register AHCI: Do not (re)map FB/CLB buffers while not running Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
commit
627f91b1f8
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@ -51,6 +51,10 @@ static void ahci_write_fis_d2h(AHCIDevice *ad, uint8_t *cmd_fis);
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static void ahci_init_d2h(AHCIDevice *ad);
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static int ahci_dma_prepare_buf(IDEDMA *dma, int is_write);
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static void ahci_commit_buf(IDEDMA *dma, uint32_t tx_bytes);
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static bool ahci_map_clb_address(AHCIDevice *ad);
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static bool ahci_map_fis_address(AHCIDevice *ad);
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static void ahci_unmap_clb_address(AHCIDevice *ad);
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static void ahci_unmap_fis_address(AHCIDevice *ad);
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static uint32_t ahci_port_read(AHCIState *s, int port, int offset)
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@ -202,25 +206,15 @@ static void ahci_port_write(AHCIState *s, int port, int offset, uint32_t val)
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switch (offset) {
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case PORT_LST_ADDR:
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pr->lst_addr = val;
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map_page(s->as, &s->dev[port].lst,
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((uint64_t)pr->lst_addr_hi << 32) | pr->lst_addr, 1024);
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s->dev[port].cur_cmd = NULL;
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break;
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case PORT_LST_ADDR_HI:
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pr->lst_addr_hi = val;
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map_page(s->as, &s->dev[port].lst,
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((uint64_t)pr->lst_addr_hi << 32) | pr->lst_addr, 1024);
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s->dev[port].cur_cmd = NULL;
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break;
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case PORT_FIS_ADDR:
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pr->fis_addr = val;
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map_page(s->as, &s->dev[port].res_fis,
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((uint64_t)pr->fis_addr_hi << 32) | pr->fis_addr, 256);
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break;
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case PORT_FIS_ADDR_HI:
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pr->fis_addr_hi = val;
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map_page(s->as, &s->dev[port].res_fis,
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((uint64_t)pr->fis_addr_hi << 32) | pr->fis_addr, 256);
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break;
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case PORT_IRQ_STAT:
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pr->irq_stat &= ~val;
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@ -231,14 +225,32 @@ static void ahci_port_write(AHCIState *s, int port, int offset, uint32_t val)
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ahci_check_irq(s);
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break;
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case PORT_CMD:
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pr->cmd = val & ~(PORT_CMD_LIST_ON | PORT_CMD_FIS_ON);
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/* Block any Read-only fields from being set;
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* including LIST_ON and FIS_ON. */
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pr->cmd = (pr->cmd & PORT_CMD_RO_MASK) | (val & ~PORT_CMD_RO_MASK);
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if (pr->cmd & PORT_CMD_START) {
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pr->cmd |= PORT_CMD_LIST_ON;
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if (ahci_map_clb_address(&s->dev[port])) {
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pr->cmd |= PORT_CMD_LIST_ON;
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} else {
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error_report("AHCI: Failed to start DMA engine: "
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"bad command list buffer address");
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}
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} else if (pr->cmd & PORT_CMD_LIST_ON) {
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ahci_unmap_clb_address(&s->dev[port]);
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pr->cmd = pr->cmd & ~(PORT_CMD_LIST_ON);
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}
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if (pr->cmd & PORT_CMD_FIS_RX) {
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pr->cmd |= PORT_CMD_FIS_ON;
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if (ahci_map_fis_address(&s->dev[port])) {
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pr->cmd |= PORT_CMD_FIS_ON;
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} else {
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error_report("AHCI: Failed to start FIS receive engine: "
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"bad FIS receive buffer address");
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}
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} else if (pr->cmd & PORT_CMD_FIS_ON) {
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ahci_unmap_fis_address(&s->dev[port]);
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pr->cmd = pr->cmd & ~(PORT_CMD_FIS_ON);
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}
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/* XXX usually the FIS would be pending on the bus here and
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@ -565,6 +577,37 @@ static void debug_print_fis(uint8_t *fis, int cmd_len)
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#endif
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}
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static bool ahci_map_fis_address(AHCIDevice *ad)
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{
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AHCIPortRegs *pr = &ad->port_regs;
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map_page(ad->hba->as, &ad->res_fis,
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((uint64_t)pr->fis_addr_hi << 32) | pr->fis_addr, 256);
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return ad->res_fis != NULL;
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}
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static void ahci_unmap_fis_address(AHCIDevice *ad)
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{
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dma_memory_unmap(ad->hba->as, ad->res_fis, 256,
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DMA_DIRECTION_FROM_DEVICE, 256);
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ad->res_fis = NULL;
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}
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static bool ahci_map_clb_address(AHCIDevice *ad)
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{
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AHCIPortRegs *pr = &ad->port_regs;
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ad->cur_cmd = NULL;
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map_page(ad->hba->as, &ad->lst,
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((uint64_t)pr->lst_addr_hi << 32) | pr->lst_addr, 1024);
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return ad->lst != NULL;
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}
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static void ahci_unmap_clb_address(AHCIDevice *ad)
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{
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dma_memory_unmap(ad->hba->as, ad->lst, 1024,
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DMA_DIRECTION_FROM_DEVICE, 1024);
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ad->lst = NULL;
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}
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static void ahci_write_fis_sdb(AHCIState *s, int port, uint32_t finished)
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{
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AHCIDevice *ad = &s->dev[port];
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@ -1360,12 +1403,9 @@ static int ahci_state_post_load(void *opaque, int version_id)
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for (i = 0; i < s->ports; i++) {
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ad = &s->dev[i];
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AHCIPortRegs *pr = &ad->port_regs;
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map_page(s->as, &ad->lst,
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((uint64_t)pr->lst_addr_hi << 32) | pr->lst_addr, 1024);
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map_page(s->as, &ad->res_fis,
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((uint64_t)pr->fis_addr_hi << 32) | pr->fis_addr, 256);
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ahci_map_clb_address(ad);
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ahci_map_fis_address(ad);
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/*
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* If an error is present, ad->busy_slot will be valid and not -1.
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* In this case, an operation is waiting to resume and will re-check
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@ -132,6 +132,8 @@
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#define PORT_CMD_ICC_PARTIAL (0x2 << 28) /* Put i/f in partial state */
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#define PORT_CMD_ICC_SLUMBER (0x6 << 28) /* Put i/f in slumber state */
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#define PORT_CMD_RO_MASK 0x007dffe0 /* Which CMD bits are read only? */
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/* ap->flags bits */
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#define AHCI_FLAG_NO_NCQ (1 << 24)
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#define AHCI_FLAG_IGN_IRQ_IF_ERR (1 << 25) /* ignore IRQ_IF_ERR */
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