target/arm: Make MPU_RBAR, MPU_RLAR banked for v8M
Make the MPU registers MPU_MAIR0 and MPU_MAIR1 banked if v8M security extensions are enabled. We can freely add more items to vmstate_m_security without breaking migration compatibility, because no CPU currently has the ARM_FEATURE_M_SECURITY bit enabled and so this subsection is not yet used by anything. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 1503414539-28762-14-git-send-email-peter.maydell@linaro.org
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@ -564,7 +564,7 @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs)
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if (region >= cpu->pmsav7_dregion) {
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if (region >= cpu->pmsav7_dregion) {
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return 0;
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return 0;
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}
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}
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return cpu->env.pmsav8.rbar[region];
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return cpu->env.pmsav8.rbar[attrs.secure][region];
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}
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}
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if (region >= cpu->pmsav7_dregion) {
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if (region >= cpu->pmsav7_dregion) {
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@ -591,7 +591,7 @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs)
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if (region >= cpu->pmsav7_dregion) {
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if (region >= cpu->pmsav7_dregion) {
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return 0;
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return 0;
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}
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}
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return cpu->env.pmsav8.rlar[region];
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return cpu->env.pmsav8.rlar[attrs.secure][region];
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}
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}
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if (region >= cpu->pmsav7_dregion) {
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if (region >= cpu->pmsav7_dregion) {
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@ -756,7 +756,7 @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value,
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if (region >= cpu->pmsav7_dregion) {
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if (region >= cpu->pmsav7_dregion) {
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return;
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return;
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}
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}
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cpu->env.pmsav8.rbar[region] = value;
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cpu->env.pmsav8.rbar[attrs.secure][region] = value;
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tlb_flush(CPU(cpu));
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tlb_flush(CPU(cpu));
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return;
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return;
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}
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}
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@ -806,7 +806,7 @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value,
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if (region >= cpu->pmsav7_dregion) {
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if (region >= cpu->pmsav7_dregion) {
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return;
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return;
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}
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}
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cpu->env.pmsav8.rlar[region] = value;
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cpu->env.pmsav8.rlar[attrs.secure][region] = value;
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tlb_flush(CPU(cpu));
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tlb_flush(CPU(cpu));
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return;
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return;
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}
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}
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@ -235,10 +235,20 @@ static void arm_cpu_reset(CPUState *s)
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if (arm_feature(env, ARM_FEATURE_PMSA)) {
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if (arm_feature(env, ARM_FEATURE_PMSA)) {
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if (cpu->pmsav7_dregion > 0) {
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if (cpu->pmsav7_dregion > 0) {
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if (arm_feature(env, ARM_FEATURE_V8)) {
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if (arm_feature(env, ARM_FEATURE_V8)) {
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memset(env->pmsav8.rbar, 0,
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memset(env->pmsav8.rbar[M_REG_NS], 0,
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sizeof(*env->pmsav8.rbar) * cpu->pmsav7_dregion);
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sizeof(*env->pmsav8.rbar[M_REG_NS])
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memset(env->pmsav8.rlar, 0,
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* cpu->pmsav7_dregion);
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sizeof(*env->pmsav8.rlar) * cpu->pmsav7_dregion);
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memset(env->pmsav8.rlar[M_REG_NS], 0,
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sizeof(*env->pmsav8.rlar[M_REG_NS])
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* cpu->pmsav7_dregion);
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if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
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memset(env->pmsav8.rbar[M_REG_S], 0,
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sizeof(*env->pmsav8.rbar[M_REG_S])
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* cpu->pmsav7_dregion);
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memset(env->pmsav8.rlar[M_REG_S], 0,
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sizeof(*env->pmsav8.rlar[M_REG_S])
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* cpu->pmsav7_dregion);
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}
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} else if (arm_feature(env, ARM_FEATURE_V7)) {
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} else if (arm_feature(env, ARM_FEATURE_V7)) {
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memset(env->pmsav7.drbar, 0,
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memset(env->pmsav7.drbar, 0,
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sizeof(*env->pmsav7.drbar) * cpu->pmsav7_dregion);
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sizeof(*env->pmsav7.drbar) * cpu->pmsav7_dregion);
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@ -825,8 +835,12 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
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if (nr) {
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if (nr) {
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if (arm_feature(env, ARM_FEATURE_V8)) {
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if (arm_feature(env, ARM_FEATURE_V8)) {
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/* PMSAv8 */
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/* PMSAv8 */
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env->pmsav8.rbar = g_new0(uint32_t, nr);
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env->pmsav8.rbar[M_REG_NS] = g_new0(uint32_t, nr);
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env->pmsav8.rlar = g_new0(uint32_t, nr);
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env->pmsav8.rlar[M_REG_NS] = g_new0(uint32_t, nr);
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if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
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env->pmsav8.rbar[M_REG_S] = g_new0(uint32_t, nr);
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env->pmsav8.rlar[M_REG_S] = g_new0(uint32_t, nr);
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}
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} else {
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} else {
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env->pmsav7.drbar = g_new0(uint32_t, nr);
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env->pmsav7.drbar = g_new0(uint32_t, nr);
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env->pmsav7.drsr = g_new0(uint32_t, nr);
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env->pmsav7.drsr = g_new0(uint32_t, nr);
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@ -543,8 +543,8 @@ typedef struct CPUARMState {
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* pmsav7.rnr (region number register)
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* pmsav7.rnr (region number register)
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* pmsav7_dregion (number of configured regions)
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* pmsav7_dregion (number of configured regions)
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*/
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*/
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uint32_t *rbar;
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uint32_t *rbar[2];
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uint32_t *rlar;
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uint32_t *rlar[2];
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uint32_t mair0[2];
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uint32_t mair0[2];
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uint32_t mair1[2];
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uint32_t mair1[2];
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} pmsav8;
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} pmsav8;
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@ -8437,6 +8437,7 @@ static bool get_phys_addr_pmsav8(CPUARMState *env, uint32_t address,
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{
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{
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ARMCPU *cpu = arm_env_get_cpu(env);
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ARMCPU *cpu = arm_env_get_cpu(env);
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bool is_user = regime_is_user(env, mmu_idx);
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bool is_user = regime_is_user(env, mmu_idx);
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uint32_t secure = regime_is_secure(env, mmu_idx);
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int n;
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int n;
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int matchregion = -1;
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int matchregion = -1;
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bool hit = false;
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bool hit = false;
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@ -8463,10 +8464,10 @@ static bool get_phys_addr_pmsav8(CPUARMState *env, uint32_t address,
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* with bits [4:0] all zeroes, but the limit address is bits
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* with bits [4:0] all zeroes, but the limit address is bits
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* [31:5] from the register with bits [4:0] all ones.
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* [31:5] from the register with bits [4:0] all ones.
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*/
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*/
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uint32_t base = env->pmsav8.rbar[n] & ~0x1f;
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uint32_t base = env->pmsav8.rbar[secure][n] & ~0x1f;
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uint32_t limit = env->pmsav8.rlar[n] | 0x1f;
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uint32_t limit = env->pmsav8.rlar[secure][n] | 0x1f;
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if (!(env->pmsav8.rlar[n] & 0x1)) {
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if (!(env->pmsav8.rlar[secure][n] & 0x1)) {
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/* Region disabled */
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/* Region disabled */
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continue;
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continue;
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}
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}
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@ -8515,8 +8516,8 @@ static bool get_phys_addr_pmsav8(CPUARMState *env, uint32_t address,
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/* hit using the background region */
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/* hit using the background region */
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get_phys_addr_pmsav7_default(env, mmu_idx, address, prot);
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get_phys_addr_pmsav7_default(env, mmu_idx, address, prot);
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} else {
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} else {
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uint32_t ap = extract32(env->pmsav8.rbar[matchregion], 1, 2);
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uint32_t ap = extract32(env->pmsav8.rbar[secure][matchregion], 1, 2);
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uint32_t xn = extract32(env->pmsav8.rbar[matchregion], 0, 1);
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uint32_t xn = extract32(env->pmsav8.rbar[secure][matchregion], 0, 1);
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if (m_is_system_region(env, address)) {
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if (m_is_system_region(env, address)) {
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/* System space is always execute never */
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/* System space is always execute never */
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@ -225,10 +225,10 @@ static const VMStateDescription vmstate_pmsav8 = {
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.minimum_version_id = 1,
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.minimum_version_id = 1,
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.needed = pmsav8_needed,
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.needed = pmsav8_needed,
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.fields = (VMStateField[]) {
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.fields = (VMStateField[]) {
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VMSTATE_VARRAY_UINT32(env.pmsav8.rbar, ARMCPU, pmsav7_dregion, 0,
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VMSTATE_VARRAY_UINT32(env.pmsav8.rbar[M_REG_NS], ARMCPU, pmsav7_dregion,
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vmstate_info_uint32, uint32_t),
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0, vmstate_info_uint32, uint32_t),
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VMSTATE_VARRAY_UINT32(env.pmsav8.rlar, ARMCPU, pmsav7_dregion, 0,
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VMSTATE_VARRAY_UINT32(env.pmsav8.rlar[M_REG_NS], ARMCPU, pmsav7_dregion,
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vmstate_info_uint32, uint32_t),
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0, vmstate_info_uint32, uint32_t),
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VMSTATE_UINT32(env.pmsav8.mair0[M_REG_NS], ARMCPU),
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VMSTATE_UINT32(env.pmsav8.mair0[M_REG_NS], ARMCPU),
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VMSTATE_UINT32(env.pmsav8.mair1[M_REG_NS], ARMCPU),
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VMSTATE_UINT32(env.pmsav8.mair1[M_REG_NS], ARMCPU),
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VMSTATE_END_OF_LIST()
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VMSTATE_END_OF_LIST()
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@ -257,6 +257,10 @@ static const VMStateDescription vmstate_m_security = {
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VMSTATE_UINT32(env.v7m.vecbase[M_REG_S], ARMCPU),
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VMSTATE_UINT32(env.v7m.vecbase[M_REG_S], ARMCPU),
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VMSTATE_UINT32(env.pmsav8.mair0[M_REG_S], ARMCPU),
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VMSTATE_UINT32(env.pmsav8.mair0[M_REG_S], ARMCPU),
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VMSTATE_UINT32(env.pmsav8.mair1[M_REG_S], ARMCPU),
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VMSTATE_UINT32(env.pmsav8.mair1[M_REG_S], ARMCPU),
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VMSTATE_VARRAY_UINT32(env.pmsav8.rbar[M_REG_S], ARMCPU, pmsav7_dregion,
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0, vmstate_info_uint32, uint32_t),
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VMSTATE_VARRAY_UINT32(env.pmsav8.rlar[M_REG_S], ARMCPU, pmsav7_dregion,
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0, vmstate_info_uint32, uint32_t),
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VMSTATE_END_OF_LIST()
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VMSTATE_END_OF_LIST()
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}
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}
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};
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};
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