Hexagon HVX (target/hexagon) macros
macros to interface with the generator macros referenced in instruction semantics Acked-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
This commit is contained in:
Taylor Simpson
parent
828a210785
commit
64458f4855
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@ -266,6 +266,10 @@ static inline void gen_pred_cancel(TCGv pred, int slot_num)
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#define fNEWREG_ST(VAL) (VAL)
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#define fVSATUVALN(N, VAL) \
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({ \
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(((int)(VAL)) < 0) ? 0 : ((1LL << (N)) - 1); \
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})
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#define fSATUVALN(N, VAL) \
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({ \
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fSET_OVERFLOW(); \
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@ -276,10 +280,16 @@ static inline void gen_pred_cancel(TCGv pred, int slot_num)
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fSET_OVERFLOW(); \
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((VAL) < 0) ? (-(1LL << ((N) - 1))) : ((1LL << ((N) - 1)) - 1); \
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})
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#define fVSATVALN(N, VAL) \
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({ \
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((VAL) < 0) ? (-(1LL << ((N) - 1))) : ((1LL << ((N) - 1)) - 1); \
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})
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#define fZXTN(N, M, VAL) (((N) != 0) ? extract64((VAL), 0, (N)) : 0LL)
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#define fSXTN(N, M, VAL) (((N) != 0) ? sextract64((VAL), 0, (N)) : 0LL)
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#define fSATN(N, VAL) \
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((fSXTN(N, 64, VAL) == (VAL)) ? (VAL) : fSATVALN(N, VAL))
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#define fVSATN(N, VAL) \
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((fSXTN(N, 64, VAL) == (VAL)) ? (VAL) : fVSATVALN(N, VAL))
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#define fADDSAT64(DST, A, B) \
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do { \
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uint64_t __a = fCAST8u(A); \
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@ -302,12 +312,18 @@ static inline void gen_pred_cancel(TCGv pred, int slot_num)
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DST = __sum; \
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} \
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} while (0)
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#define fVSATUN(N, VAL) \
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((fZXTN(N, 64, VAL) == (VAL)) ? (VAL) : fVSATUVALN(N, VAL))
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#define fSATUN(N, VAL) \
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((fZXTN(N, 64, VAL) == (VAL)) ? (VAL) : fSATUVALN(N, VAL))
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#define fSATH(VAL) (fSATN(16, VAL))
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#define fSATUH(VAL) (fSATUN(16, VAL))
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#define fVSATH(VAL) (fVSATN(16, VAL))
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#define fVSATUH(VAL) (fVSATUN(16, VAL))
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#define fSATUB(VAL) (fSATUN(8, VAL))
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#define fSATB(VAL) (fSATN(8, VAL))
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#define fVSATUB(VAL) (fVSATUN(8, VAL))
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#define fVSATB(VAL) (fVSATN(8, VAL))
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#define fIMMEXT(IMM) (IMM = IMM)
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#define fMUST_IMMEXT(IMM) fIMMEXT(IMM)
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@ -414,6 +430,8 @@ static inline TCGv gen_read_ireg(TCGv result, TCGv val, int shift)
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#define fCAST4s(A) ((int32_t)(A))
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#define fCAST8u(A) ((uint64_t)(A))
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#define fCAST8s(A) ((int64_t)(A))
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#define fCAST2_2s(A) ((int16_t)(A))
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#define fCAST2_2u(A) ((uint16_t)(A))
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#define fCAST4_4s(A) ((int32_t)(A))
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#define fCAST4_4u(A) ((uint32_t)(A))
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#define fCAST4_8s(A) ((int64_t)((int32_t)(A)))
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@ -510,7 +528,9 @@ static inline TCGv gen_read_ireg(TCGv result, TCGv val, int shift)
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#define fPM_M(REG, MVAL) do { REG = REG + (MVAL); } while (0)
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#endif
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#define fSCALE(N, A) (((int64_t)(A)) << N)
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#define fVSATW(A) fVSATN(32, ((long long)A))
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#define fSATW(A) fSATN(32, ((long long)A))
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#define fVSAT(A) fVSATN(32, (A))
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#define fSAT(A) fSATN(32, (A))
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#define fSAT_ORIG_SHL(A, ORIG_REG) \
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((((int32_t)((fSAT(A)) ^ ((int32_t)(ORIG_REG)))) < 0) \
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@ -647,12 +667,14 @@ static inline TCGv gen_read_ireg(TCGv result, TCGv val, int shift)
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fSETBIT(j, DST, VAL); \
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} \
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} while (0)
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#define fCOUNTONES_2(VAL) ctpop16(VAL)
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#define fCOUNTONES_4(VAL) ctpop32(VAL)
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#define fCOUNTONES_8(VAL) ctpop64(VAL)
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#define fBREV_8(VAL) revbit64(VAL)
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#define fBREV_4(VAL) revbit32(VAL)
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#define fCL1_8(VAL) clo64(VAL)
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#define fCL1_4(VAL) clo32(VAL)
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#define fCL1_2(VAL) (clz32(~(uint16_t)(VAL) & 0xffff) - 16)
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#define fINTERLEAVE(ODD, EVEN) interleave(ODD, EVEN)
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#define fDEINTERLEAVE(MIXED) deinterleave(MIXED)
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#define fHIDE(A) A
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354
target/hexagon/mmvec/macros.h
Normal file
354
target/hexagon/mmvec/macros.h
Normal file
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@ -0,0 +1,354 @@
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/*
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* Copyright(c) 2019-2021 Qualcomm Innovation Center, Inc. All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef HEXAGON_MMVEC_MACROS_H
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#define HEXAGON_MMVEC_MACROS_H
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#include "qemu/osdep.h"
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#include "qemu/host-utils.h"
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#include "arch.h"
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#include "mmvec/system_ext_mmvec.h"
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#ifndef QEMU_GENERATE
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#define VdV (*(MMVector *)(VdV_void))
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#define VsV (*(MMVector *)(VsV_void))
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#define VuV (*(MMVector *)(VuV_void))
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#define VvV (*(MMVector *)(VvV_void))
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#define VwV (*(MMVector *)(VwV_void))
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#define VxV (*(MMVector *)(VxV_void))
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#define VyV (*(MMVector *)(VyV_void))
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#define VddV (*(MMVectorPair *)(VddV_void))
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#define VuuV (*(MMVectorPair *)(VuuV_void))
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#define VvvV (*(MMVectorPair *)(VvvV_void))
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#define VxxV (*(MMVectorPair *)(VxxV_void))
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#define QeV (*(MMQReg *)(QeV_void))
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#define QdV (*(MMQReg *)(QdV_void))
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#define QsV (*(MMQReg *)(QsV_void))
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#define QtV (*(MMQReg *)(QtV_void))
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#define QuV (*(MMQReg *)(QuV_void))
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#define QvV (*(MMQReg *)(QvV_void))
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#define QxV (*(MMQReg *)(QxV_void))
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#endif
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#define LOG_VTCM_BYTE(VA, MASK, VAL, IDX) \
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do { \
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env->vtcm_log.data.ub[IDX] = (VAL); \
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if (MASK) { \
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set_bit((IDX), env->vtcm_log.mask); \
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} else { \
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clear_bit((IDX), env->vtcm_log.mask); \
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} \
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env->vtcm_log.va[IDX] = (VA); \
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} while (0)
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#define fNOTQ(VAL) \
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({ \
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MMQReg _ret; \
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int _i_; \
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for (_i_ = 0; _i_ < fVECSIZE() / 64; _i_++) { \
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_ret.ud[_i_] = ~VAL.ud[_i_]; \
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} \
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_ret;\
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})
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#define fGETQBITS(REG, WIDTH, MASK, BITNO) \
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((MASK) & (REG.w[(BITNO) >> 5] >> ((BITNO) & 0x1f)))
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#define fGETQBIT(REG, BITNO) fGETQBITS(REG, 1, 1, BITNO)
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#define fGENMASKW(QREG, IDX) \
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(((fGETQBIT(QREG, (IDX * 4 + 0)) ? 0xFF : 0x0) << 0) | \
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((fGETQBIT(QREG, (IDX * 4 + 1)) ? 0xFF : 0x0) << 8) | \
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((fGETQBIT(QREG, (IDX * 4 + 2)) ? 0xFF : 0x0) << 16) | \
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((fGETQBIT(QREG, (IDX * 4 + 3)) ? 0xFF : 0x0) << 24))
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#define fGETNIBBLE(IDX, SRC) (fSXTN(4, 8, (SRC >> (4 * IDX)) & 0xF))
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#define fGETCRUMB(IDX, SRC) (fSXTN(2, 8, (SRC >> (2 * IDX)) & 0x3))
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#define fGETCRUMB_SYMMETRIC(IDX, SRC) \
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((fGETCRUMB(IDX, SRC) >= 0 ? (2 - fGETCRUMB(IDX, SRC)) \
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: fGETCRUMB(IDX, SRC)))
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#define fGENMASKH(QREG, IDX) \
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(((fGETQBIT(QREG, (IDX * 2 + 0)) ? 0xFF : 0x0) << 0) | \
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((fGETQBIT(QREG, (IDX * 2 + 1)) ? 0xFF : 0x0) << 8))
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#define fGETMASKW(VREG, QREG, IDX) (VREG.w[IDX] & fGENMASKW((QREG), IDX))
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#define fGETMASKH(VREG, QREG, IDX) (VREG.h[IDX] & fGENMASKH((QREG), IDX))
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#define fCONDMASK8(QREG, IDX, YESVAL, NOVAL) \
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(fGETQBIT(QREG, IDX) ? (YESVAL) : (NOVAL))
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#define fCONDMASK16(QREG, IDX, YESVAL, NOVAL) \
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((fGENMASKH(QREG, IDX) & (YESVAL)) | \
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(fGENMASKH(fNOTQ(QREG), IDX) & (NOVAL)))
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#define fCONDMASK32(QREG, IDX, YESVAL, NOVAL) \
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((fGENMASKW(QREG, IDX) & (YESVAL)) | \
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(fGENMASKW(fNOTQ(QREG), IDX) & (NOVAL)))
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#define fSETQBITS(REG, WIDTH, MASK, BITNO, VAL) \
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do { \
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uint32_t __TMP = (VAL); \
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REG.w[(BITNO) >> 5] &= ~((MASK) << ((BITNO) & 0x1f)); \
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REG.w[(BITNO) >> 5] |= (((__TMP) & (MASK)) << ((BITNO) & 0x1f)); \
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} while (0)
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#define fSETQBIT(REG, BITNO, VAL) fSETQBITS(REG, 1, 1, BITNO, VAL)
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#define fVBYTES() (fVECSIZE())
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#define fVALIGN(ADDR, LOG2_ALIGNMENT) (ADDR = ADDR & ~(LOG2_ALIGNMENT - 1))
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#define fVLASTBYTE(ADDR, LOG2_ALIGNMENT) (ADDR = ADDR | (LOG2_ALIGNMENT - 1))
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#define fVELEM(WIDTH) ((fVECSIZE() * 8) / WIDTH)
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#define fVECLOGSIZE() (7)
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#define fVECSIZE() (1 << fVECLOGSIZE())
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#define fSWAPB(A, B) do { uint8_t tmp = A; A = B; B = tmp; } while (0)
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#define fV_AL_CHECK(EA, MASK) \
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if ((EA) & (MASK)) { \
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warn("aligning misaligned vector. EA=%08x", (EA)); \
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}
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#define fSCATTER_INIT(REGION_START, LENGTH, ELEMENT_SIZE) \
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mem_vector_scatter_init(env)
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#define fGATHER_INIT(REGION_START, LENGTH, ELEMENT_SIZE) \
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mem_vector_gather_init(env)
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#define fSCATTER_FINISH(OP)
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#define fGATHER_FINISH()
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#define fLOG_SCATTER_OP(SIZE) \
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do { \
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env->vtcm_log.op = true; \
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env->vtcm_log.op_size = SIZE; \
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} while (0)
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#define fVLOG_VTCM_WORD_INCREMENT(EA, OFFSET, INC, IDX, ALIGNMENT, LEN) \
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do { \
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int log_byte = 0; \
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target_ulong va = EA; \
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target_ulong va_high = EA + LEN; \
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for (int i0 = 0; i0 < 4; i0++) { \
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log_byte = (va + i0) <= va_high; \
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LOG_VTCM_BYTE(va + i0, log_byte, INC. ub[4 * IDX + i0], \
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4 * IDX + i0); \
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} \
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} while (0)
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#define fVLOG_VTCM_HALFWORD_INCREMENT(EA, OFFSET, INC, IDX, ALIGNMENT, LEN) \
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do { \
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int log_byte = 0; \
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target_ulong va = EA; \
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target_ulong va_high = EA + LEN; \
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for (int i0 = 0; i0 < 2; i0++) { \
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log_byte = (va + i0) <= va_high; \
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LOG_VTCM_BYTE(va + i0, log_byte, INC.ub[2 * IDX + i0], \
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2 * IDX + i0); \
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} \
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} while (0)
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#define fVLOG_VTCM_HALFWORD_INCREMENT_DV(EA, OFFSET, INC, IDX, IDX2, IDX_H, \
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ALIGNMENT, LEN) \
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do { \
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int log_byte = 0; \
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target_ulong va = EA; \
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target_ulong va_high = EA + LEN; \
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for (int i0 = 0; i0 < 2; i0++) { \
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log_byte = (va + i0) <= va_high; \
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LOG_VTCM_BYTE(va + i0, log_byte, INC.ub[2 * IDX + i0], \
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2 * IDX + i0); \
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} \
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} while (0)
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/* NOTE - Will this always be tmp_VRegs[0]; */
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#define GATHER_FUNCTION(EA, OFFSET, IDX, LEN, ELEMENT_SIZE, BANK_IDX, QVAL) \
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do { \
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int i0; \
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target_ulong va = EA; \
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target_ulong va_high = EA + LEN; \
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uintptr_t ra = GETPC(); \
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int log_bank = 0; \
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int log_byte = 0; \
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for (i0 = 0; i0 < ELEMENT_SIZE; i0++) { \
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log_byte = ((va + i0) <= va_high) && QVAL; \
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log_bank |= (log_byte << i0); \
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uint8_t B; \
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B = cpu_ldub_data_ra(env, EA + i0, ra); \
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env->tmp_VRegs[0].ub[ELEMENT_SIZE * IDX + i0] = B; \
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LOG_VTCM_BYTE(va + i0, log_byte, B, ELEMENT_SIZE * IDX + i0); \
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} \
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} while (0)
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#define fVLOG_VTCM_GATHER_WORD(EA, OFFSET, IDX, LEN) \
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do { \
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GATHER_FUNCTION(EA, OFFSET, IDX, LEN, 4, IDX, 1); \
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} while (0)
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#define fVLOG_VTCM_GATHER_HALFWORD(EA, OFFSET, IDX, LEN) \
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do { \
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GATHER_FUNCTION(EA, OFFSET, IDX, LEN, 2, IDX, 1); \
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} while (0)
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#define fVLOG_VTCM_GATHER_HALFWORD_DV(EA, OFFSET, IDX, IDX2, IDX_H, LEN) \
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do { \
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GATHER_FUNCTION(EA, OFFSET, IDX, LEN, 2, (2 * IDX2 + IDX_H), 1); \
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} while (0)
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#define fVLOG_VTCM_GATHER_WORDQ(EA, OFFSET, IDX, Q, LEN) \
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do { \
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GATHER_FUNCTION(EA, OFFSET, IDX, LEN, 4, IDX, \
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fGETQBIT(QsV, 4 * IDX + i0)); \
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} while (0)
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#define fVLOG_VTCM_GATHER_HALFWORDQ(EA, OFFSET, IDX, Q, LEN) \
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do { \
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GATHER_FUNCTION(EA, OFFSET, IDX, LEN, 2, IDX, \
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fGETQBIT(QsV, 2 * IDX + i0)); \
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} while (0)
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#define fVLOG_VTCM_GATHER_HALFWORDQ_DV(EA, OFFSET, IDX, IDX2, IDX_H, Q, LEN) \
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do { \
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GATHER_FUNCTION(EA, OFFSET, IDX, LEN, 2, (2 * IDX2 + IDX_H), \
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fGETQBIT(QsV, 2 * IDX + i0)); \
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} while (0)
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#define SCATTER_OP_WRITE_TO_MEM(TYPE) \
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do { \
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uintptr_t ra = GETPC(); \
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for (int i = 0; i < sizeof(MMVector); i += sizeof(TYPE)) { \
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if (test_bit(i, env->vtcm_log.mask)) { \
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TYPE dst = 0; \
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TYPE inc = 0; \
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for (int j = 0; j < sizeof(TYPE); j++) { \
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uint8_t val; \
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val = cpu_ldub_data_ra(env, env->vtcm_log.va[i + j], ra); \
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dst |= val << (8 * j); \
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inc |= env->vtcm_log.data.ub[j + i] << (8 * j); \
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clear_bit(j + i, env->vtcm_log.mask); \
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env->vtcm_log.data.ub[j + i] = 0; \
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} \
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dst += inc; \
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for (int j = 0; j < sizeof(TYPE); j++) { \
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cpu_stb_data_ra(env, env->vtcm_log.va[i + j], \
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(dst >> (8 * j)) & 0xFF, ra); \
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} \
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} \
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} \
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} while (0)
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#define SCATTER_OP_PROBE_MEM(TYPE, MMU_IDX, RETADDR) \
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do { \
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for (int i = 0; i < sizeof(MMVector); i += sizeof(TYPE)) { \
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if (test_bit(i, env->vtcm_log.mask)) { \
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for (int j = 0; j < sizeof(TYPE); j++) { \
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probe_read(env, env->vtcm_log.va[i + j], 1, \
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MMU_IDX, RETADDR); \
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probe_write(env, env->vtcm_log.va[i + j], 1, \
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MMU_IDX, RETADDR); \
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} \
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} \
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} \
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} while (0)
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#define SCATTER_FUNCTION(EA, OFFSET, IDX, LEN, ELEM_SIZE, BANK_IDX, QVAL, IN) \
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do { \
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int i0; \
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target_ulong va = EA; \
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target_ulong va_high = EA + LEN; \
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int log_bank = 0; \
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int log_byte = 0; \
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for (i0 = 0; i0 < ELEM_SIZE; i0++) { \
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log_byte = ((va + i0) <= va_high) && QVAL; \
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log_bank |= (log_byte << i0); \
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LOG_VTCM_BYTE(va + i0, log_byte, IN.ub[ELEM_SIZE * IDX + i0], \
|
||||
ELEM_SIZE * IDX + i0); \
|
||||
} \
|
||||
} while (0)
|
||||
#define fVLOG_VTCM_HALFWORD(EA, OFFSET, IN, IDX, LEN) \
|
||||
do { \
|
||||
SCATTER_FUNCTION(EA, OFFSET, IDX, LEN, 2, IDX, 1, IN); \
|
||||
} while (0)
|
||||
#define fVLOG_VTCM_WORD(EA, OFFSET, IN, IDX, LEN) \
|
||||
do { \
|
||||
SCATTER_FUNCTION(EA, OFFSET, IDX, LEN, 4, IDX, 1, IN); \
|
||||
} while (0)
|
||||
#define fVLOG_VTCM_HALFWORDQ(EA, OFFSET, IN, IDX, Q, LEN) \
|
||||
do { \
|
||||
SCATTER_FUNCTION(EA, OFFSET, IDX, LEN, 2, IDX, \
|
||||
fGETQBIT(QsV, 2 * IDX + i0), IN); \
|
||||
} while (0)
|
||||
#define fVLOG_VTCM_WORDQ(EA, OFFSET, IN, IDX, Q, LEN) \
|
||||
do { \
|
||||
SCATTER_FUNCTION(EA, OFFSET, IDX, LEN, 4, IDX, \
|
||||
fGETQBIT(QsV, 4 * IDX + i0), IN); \
|
||||
} while (0)
|
||||
#define fVLOG_VTCM_HALFWORD_DV(EA, OFFSET, IN, IDX, IDX2, IDX_H, LEN) \
|
||||
do { \
|
||||
SCATTER_FUNCTION(EA, OFFSET, IDX, LEN, 2, \
|
||||
(2 * IDX2 + IDX_H), 1, IN); \
|
||||
} while (0)
|
||||
#define fVLOG_VTCM_HALFWORDQ_DV(EA, OFFSET, IN, IDX, Q, IDX2, IDX_H, LEN) \
|
||||
do { \
|
||||
SCATTER_FUNCTION(EA, OFFSET, IDX, LEN, 2, (2 * IDX2 + IDX_H), \
|
||||
fGETQBIT(QsV, 2 * IDX + i0), IN); \
|
||||
} while (0)
|
||||
#define fSTORERELEASE(EA, TYPE) \
|
||||
do { \
|
||||
fV_AL_CHECK(EA, fVECSIZE() - 1); \
|
||||
} while (0)
|
||||
#ifdef QEMU_GENERATE
|
||||
#define fLOADMMV(EA, DST) gen_vreg_load(ctx, DST##_off, EA, true)
|
||||
#endif
|
||||
#ifdef QEMU_GENERATE
|
||||
#define fLOADMMVU(EA, DST) gen_vreg_load(ctx, DST##_off, EA, false)
|
||||
#endif
|
||||
#ifdef QEMU_GENERATE
|
||||
#define fSTOREMMV(EA, SRC) \
|
||||
gen_vreg_store(ctx, insn, pkt, EA, SRC##_off, insn->slot, true)
|
||||
#endif
|
||||
#ifdef QEMU_GENERATE
|
||||
#define fSTOREMMVQ(EA, SRC, MASK) \
|
||||
gen_vreg_masked_store(ctx, EA, SRC##_off, MASK##_off, insn->slot, false)
|
||||
#endif
|
||||
#ifdef QEMU_GENERATE
|
||||
#define fSTOREMMVNQ(EA, SRC, MASK) \
|
||||
gen_vreg_masked_store(ctx, EA, SRC##_off, MASK##_off, insn->slot, true)
|
||||
#endif
|
||||
#ifdef QEMU_GENERATE
|
||||
#define fSTOREMMVU(EA, SRC) \
|
||||
gen_vreg_store(ctx, insn, pkt, EA, SRC##_off, insn->slot, false)
|
||||
#endif
|
||||
#define fVFOREACH(WIDTH, VAR) for (VAR = 0; VAR < fVELEM(WIDTH); VAR++)
|
||||
#define fVARRAY_ELEMENT_ACCESS(ARRAY, TYPE, INDEX) \
|
||||
ARRAY.v[(INDEX) / (fVECSIZE() / (sizeof(ARRAY.TYPE[0])))].TYPE[(INDEX) % \
|
||||
(fVECSIZE() / (sizeof(ARRAY.TYPE[0])))]
|
||||
|
||||
#define fVSATDW(U, V) fVSATW(((((long long)U) << 32) | fZXTN(32, 64, V)))
|
||||
#define fVASL_SATHI(U, V) fVSATW(((U) << 1) | ((V) >> 31))
|
||||
#define fVUADDSAT(WIDTH, U, V) \
|
||||
fVSATUN(WIDTH, fZXTN(WIDTH, 2 * WIDTH, U) + fZXTN(WIDTH, 2 * WIDTH, V))
|
||||
#define fVSADDSAT(WIDTH, U, V) \
|
||||
fVSATN(WIDTH, fSXTN(WIDTH, 2 * WIDTH, U) + fSXTN(WIDTH, 2 * WIDTH, V))
|
||||
#define fVUSUBSAT(WIDTH, U, V) \
|
||||
fVSATUN(WIDTH, fZXTN(WIDTH, 2 * WIDTH, U) - fZXTN(WIDTH, 2 * WIDTH, V))
|
||||
#define fVSSUBSAT(WIDTH, U, V) \
|
||||
fVSATN(WIDTH, fSXTN(WIDTH, 2 * WIDTH, U) - fSXTN(WIDTH, 2 * WIDTH, V))
|
||||
#define fVAVGU(WIDTH, U, V) \
|
||||
((fZXTN(WIDTH, 2 * WIDTH, U) + fZXTN(WIDTH, 2 * WIDTH, V)) >> 1)
|
||||
#define fVAVGURND(WIDTH, U, V) \
|
||||
((fZXTN(WIDTH, 2 * WIDTH, U) + fZXTN(WIDTH, 2 * WIDTH, V) + 1) >> 1)
|
||||
#define fVNAVGU(WIDTH, U, V) \
|
||||
((fZXTN(WIDTH, 2 * WIDTH, U) - fZXTN(WIDTH, 2 * WIDTH, V)) >> 1)
|
||||
#define fVNAVGURNDSAT(WIDTH, U, V) \
|
||||
fVSATUN(WIDTH, ((fZXTN(WIDTH, 2 * WIDTH, U) - \
|
||||
fZXTN(WIDTH, 2 * WIDTH, V) + 1) >> 1))
|
||||
#define fVAVGS(WIDTH, U, V) \
|
||||
((fSXTN(WIDTH, 2 * WIDTH, U) + fSXTN(WIDTH, 2 * WIDTH, V)) >> 1)
|
||||
#define fVAVGSRND(WIDTH, U, V) \
|
||||
((fSXTN(WIDTH, 2 * WIDTH, U) + fSXTN(WIDTH, 2 * WIDTH, V) + 1) >> 1)
|
||||
#define fVNAVGS(WIDTH, U, V) \
|
||||
((fSXTN(WIDTH, 2 * WIDTH, U) - fSXTN(WIDTH, 2 * WIDTH, V)) >> 1)
|
||||
#define fVNAVGSRND(WIDTH, U, V) \
|
||||
((fSXTN(WIDTH, 2 * WIDTH, U) - fSXTN(WIDTH, 2 * WIDTH, V) + 1) >> 1)
|
||||
#define fVNAVGSRNDSAT(WIDTH, U, V) \
|
||||
fVSATN(WIDTH, ((fSXTN(WIDTH, 2 * WIDTH, U) - \
|
||||
fSXTN(WIDTH, 2 * WIDTH, V) + 1) >> 1))
|
||||
#define fVNOROUND(VAL, SHAMT) VAL
|
||||
#define fVNOSAT(VAL) VAL
|
||||
#define fVROUND(VAL, SHAMT) \
|
||||
((VAL) + (((SHAMT) > 0) ? (1LL << ((SHAMT) - 1)) : 0))
|
||||
#define fCARRY_FROM_ADD32(A, B, C) \
|
||||
(((fZXTN(32, 64, A) + fZXTN(32, 64, B) + C) >> 32) & 1)
|
||||
#define fUARCH_NOTE_PUMP_4X()
|
||||
#define fUARCH_NOTE_PUMP_2X()
|
||||
|
||||
#define IV1DEAD()
|
||||
#endif
|
||||
Loading…
Reference in a new issue