hw/intc/arm_gic: Fix GIC_SET_LEVEL
The GIC_SET_LEVEL macro unfortunately overwrote the entire level bitmask instead of just or'ing on the necessary bits, causing active level PPIs on a core to clear PPIs on other cores. Cc: qemu-stable@nongnu.org Reported-by: Rob Herring <rob.herring@linaro.org> Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org> Message-id: 1393031030-8692-1-git-send-email-christoffer.dall@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@ -40,7 +40,7 @@
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#define GIC_SET_MODEL(irq) s->irq_state[irq].model = true
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#define GIC_SET_MODEL(irq) s->irq_state[irq].model = true
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#define GIC_CLEAR_MODEL(irq) s->irq_state[irq].model = false
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#define GIC_CLEAR_MODEL(irq) s->irq_state[irq].model = false
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#define GIC_TEST_MODEL(irq) s->irq_state[irq].model
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#define GIC_TEST_MODEL(irq) s->irq_state[irq].model
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#define GIC_SET_LEVEL(irq, cm) s->irq_state[irq].level = (cm)
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#define GIC_SET_LEVEL(irq, cm) s->irq_state[irq].level |= (cm)
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#define GIC_CLEAR_LEVEL(irq, cm) s->irq_state[irq].level &= ~(cm)
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#define GIC_CLEAR_LEVEL(irq, cm) s->irq_state[irq].level &= ~(cm)
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#define GIC_TEST_LEVEL(irq, cm) ((s->irq_state[irq].level & (cm)) != 0)
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#define GIC_TEST_LEVEL(irq, cm) ((s->irq_state[irq].level & (cm)) != 0)
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#define GIC_SET_EDGE_TRIGGER(irq) s->irq_state[irq].edge_trigger = true
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#define GIC_SET_EDGE_TRIGGER(irq) s->irq_state[irq].edge_trigger = true
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