hw/net: cadence_gem: Add a new 'phy-addr' property
At present the PHY address of the PHY connected to GEM is hard-coded to either 23 (BOARD_PHY_ADDRESS) or 0. This might not be the case for all boards. Add a new 'phy-addr' property so that board can specify the PHY address for each GEM instance. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <1598924352-89526-12-git-send-email-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
parent
7124e27bb8
commit
64ac13633f
|
@ -1446,7 +1446,7 @@ static uint64_t gem_read(void *opaque, hwaddr offset, unsigned size)
|
|||
uint32_t phy_addr, reg_num;
|
||||
|
||||
phy_addr = (retval & GEM_PHYMNTNC_ADDR) >> GEM_PHYMNTNC_ADDR_SHFT;
|
||||
if (phy_addr == BOARD_PHY_ADDRESS || phy_addr == 0) {
|
||||
if (phy_addr == s->phy_addr || phy_addr == 0) {
|
||||
reg_num = (retval & GEM_PHYMNTNC_REG) >> GEM_PHYMNTNC_REG_SHIFT;
|
||||
retval &= 0xFFFF0000;
|
||||
retval |= gem_phy_read(s, reg_num);
|
||||
|
@ -1569,7 +1569,7 @@ static void gem_write(void *opaque, hwaddr offset, uint64_t val,
|
|||
uint32_t phy_addr, reg_num;
|
||||
|
||||
phy_addr = (val & GEM_PHYMNTNC_ADDR) >> GEM_PHYMNTNC_ADDR_SHFT;
|
||||
if (phy_addr == BOARD_PHY_ADDRESS || phy_addr == 0) {
|
||||
if (phy_addr == s->phy_addr || phy_addr == 0) {
|
||||
reg_num = (val & GEM_PHYMNTNC_REG) >> GEM_PHYMNTNC_REG_SHIFT;
|
||||
gem_phy_write(s, reg_num, val);
|
||||
}
|
||||
|
@ -1682,6 +1682,7 @@ static Property gem_properties[] = {
|
|||
DEFINE_NIC_PROPERTIES(CadenceGEMState, conf),
|
||||
DEFINE_PROP_UINT32("revision", CadenceGEMState, revision,
|
||||
GEM_MODID_VALUE),
|
||||
DEFINE_PROP_UINT8("phy-addr", CadenceGEMState, phy_addr, BOARD_PHY_ADDRESS),
|
||||
DEFINE_PROP_UINT8("num-priority-queues", CadenceGEMState,
|
||||
num_priority_queues, 1),
|
||||
DEFINE_PROP_UINT8("num-type1-screeners", CadenceGEMState,
|
||||
|
|
|
@ -73,6 +73,8 @@ typedef struct CadenceGEMState {
|
|||
/* Mask of register bits which are write 1 to clear */
|
||||
uint32_t regs_w1c[CADENCE_GEM_MAXREG];
|
||||
|
||||
/* PHY address */
|
||||
uint8_t phy_addr;
|
||||
/* PHY registers backing store */
|
||||
uint16_t phy_regs[32];
|
||||
|
||||
|
|
Loading…
Reference in a new issue