net/cadence_gem: Implement SAR (de)activation
The Specific address registers can be enabled or disabled by software. QEMU was assuming they were always enabled. Implement the disable/enable feature. SARs are disabled by writing to the lower half register. They are re-enabled by then writing the upper half. Reported-by: Deepika Dhamija <deepika@xilinx.com> Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 49efd1f7450af8f980b967d3054245bae137866c.1386136219.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@ -382,6 +382,7 @@ typedef struct GemState {
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unsigned rx_desc[2];
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unsigned rx_desc[2];
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bool sar_active[4];
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} GemState;
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} GemState;
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/* The broadcast MAC address: 0xFFFFFFFFFFFF */
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/* The broadcast MAC address: 0xFFFFFFFFFFFF */
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@ -609,7 +610,7 @@ static int gem_mac_address_filter(GemState *s, const uint8_t *packet)
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/* Check all 4 specific addresses */
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/* Check all 4 specific addresses */
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gem_spaddr = (uint8_t *)&(s->regs[GEM_SPADDR1LO]);
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gem_spaddr = (uint8_t *)&(s->regs[GEM_SPADDR1LO]);
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for (i = 3; i >= 0; i--) {
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for (i = 3; i >= 0; i--) {
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if (!memcmp(packet, gem_spaddr + 8 * i, 6)) {
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if (s->sar_active[i] && !memcmp(packet, gem_spaddr + 8 * i, 6)) {
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return GEM_RX_SAR_ACCEPT + i;
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return GEM_RX_SAR_ACCEPT + i;
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}
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}
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}
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}
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@ -983,6 +984,7 @@ static void gem_phy_reset(GemState *s)
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static void gem_reset(DeviceState *d)
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static void gem_reset(DeviceState *d)
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{
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{
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int i;
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GemState *s = GEM(d);
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GemState *s = GEM(d);
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DB_PRINT("\n");
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DB_PRINT("\n");
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@ -1002,6 +1004,10 @@ static void gem_reset(DeviceState *d)
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s->regs[GEM_DESCONF5] = 0x002f2145;
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s->regs[GEM_DESCONF5] = 0x002f2145;
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s->regs[GEM_DESCONF6] = 0x00000200;
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s->regs[GEM_DESCONF6] = 0x00000200;
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for (i = 0; i < 4; i++) {
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s->sar_active[i] = false;
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}
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gem_phy_reset(s);
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gem_phy_reset(s);
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gem_update_int_status(s);
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gem_update_int_status(s);
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@ -1151,6 +1157,18 @@ static void gem_write(void *opaque, hwaddr offset, uint64_t val,
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s->regs[GEM_IMR] |= val;
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s->regs[GEM_IMR] |= val;
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gem_update_int_status(s);
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gem_update_int_status(s);
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break;
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break;
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case GEM_SPADDR1LO:
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case GEM_SPADDR2LO:
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case GEM_SPADDR3LO:
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case GEM_SPADDR4LO:
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s->sar_active[(offset - GEM_SPADDR1LO) / 2] = false;
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break;
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case GEM_SPADDR1HI:
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case GEM_SPADDR2HI:
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case GEM_SPADDR3HI:
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case GEM_SPADDR4HI:
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s->sar_active[(offset - GEM_SPADDR1HI) / 2] = true;
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break;
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case GEM_PHYMNTNC:
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case GEM_PHYMNTNC:
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if (val & GEM_PHYMNTNC_OP_W) {
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if (val & GEM_PHYMNTNC_OP_W) {
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uint32_t phy_addr, reg_num;
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uint32_t phy_addr, reg_num;
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@ -1218,15 +1236,16 @@ static int gem_init(SysBusDevice *sbd)
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static const VMStateDescription vmstate_cadence_gem = {
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static const VMStateDescription vmstate_cadence_gem = {
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.name = "cadence_gem",
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.name = "cadence_gem",
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.version_id = 1,
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.version_id = 2,
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.minimum_version_id = 1,
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.minimum_version_id = 2,
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.minimum_version_id_old = 1,
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.minimum_version_id_old = 2,
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.fields = (VMStateField[]) {
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.fields = (VMStateField[]) {
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VMSTATE_UINT32_ARRAY(regs, GemState, GEM_MAXREG),
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VMSTATE_UINT32_ARRAY(regs, GemState, GEM_MAXREG),
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VMSTATE_UINT16_ARRAY(phy_regs, GemState, 32),
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VMSTATE_UINT16_ARRAY(phy_regs, GemState, 32),
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VMSTATE_UINT8(phy_loop, GemState),
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VMSTATE_UINT8(phy_loop, GemState),
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VMSTATE_UINT32(rx_desc_addr, GemState),
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VMSTATE_UINT32(rx_desc_addr, GemState),
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VMSTATE_UINT32(tx_desc_addr, GemState),
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VMSTATE_UINT32(tx_desc_addr, GemState),
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VMSTATE_BOOL_ARRAY(sar_active, GemState, 4),
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}
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}
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};
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};
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