Queued TCG patches
-----BEGIN PGP SIGNATURE----- iQEcBAABAgAGBQJZYy1gAAoJEK0ScMxN0CebY9gH/A6jcmXNdaG6bWLtOiCXy+gh uRs5jvy7vh5s4+tIUMuJFA6f1dEpoTv/jl7KEM8eA2xJfLKDxKCOnhQBWYL4Kekx PLinjJ4mPtN0R1Da2WgX9qmGpW2RCktITgiwKzM7VPznZ7+fAutfPvOyWe/KpUQ2 gEJq3jUEC0p/5AGTY/t/Ek1P8Hlu5EVTdCzzfIUtOPCkI/KelMqjkGHu6dNJieKT Tjoe+crx06xFBedb8WJsIEBICFy7J4JXSMScd6L374xyj0rj5LmAXuUg6SlU/FTC jLwnqEXSuFPEgpd2oKK9qnw1CUvHAqxJQLXGeA7E8Ic4c+GmAh0q5HtlSyb11sY= =qJgI -----END PGP SIGNATURE----- Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20170709' into staging Queued TCG patches # gpg: Signature made Mon 10 Jul 2017 08:31:44 BST # gpg: using RSA key 0xAD1270CC4DD0279B # gpg: Good signature from "Richard Henderson <rth7680@gmail.com>" # gpg: aka "Richard Henderson <rth@redhat.com>" # gpg: aka "Richard Henderson <rth@twiddle.net>" # Primary key fingerprint: 9CB1 8DDA F8E8 49AD 2AFC 16A4 AD12 70CC 4DD0 279B * remotes/rth/tags/pull-tcg-20170709: tcg/mips: Bugfix for crash when running program with qemu-i386. util/cacheinfo: Fix warning generated by clang tcg/aarch64: Enable indirect jump path using LDR (literal) tcg/aarch64: Use ADRP+ADD to compute target address tcg/aarch64: Introduce and use long branch to register Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
commit
6580476a14
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@ -504,7 +504,7 @@ static inline PageDesc *page_find(tb_page_addr_t index)
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#elif defined(__powerpc__)
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# define MAX_CODE_GEN_BUFFER_SIZE (32u * 1024 * 1024)
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#elif defined(__aarch64__)
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# define MAX_CODE_GEN_BUFFER_SIZE (128ul * 1024 * 1024)
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# define MAX_CODE_GEN_BUFFER_SIZE (2ul * 1024 * 1024 * 1024)
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#elif defined(__s390x__)
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/* We have a +- 4GB range on the branches; leave some slop. */
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# define MAX_CODE_GEN_BUFFER_SIZE (3ul * 1024 * 1024 * 1024)
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@ -269,6 +269,8 @@ typedef enum {
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I3207_BLR = 0xd63f0000,
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I3207_RET = 0xd65f0000,
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/* Load literal for loading the address at pc-relative offset */
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I3305_LDR = 0x58000000,
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/* Load/store register. Described here as 3.3.12, but the helper
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that emits them can transform to 3.3.10 or 3.3.13. */
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I3312_STRB = 0x38000000 | LDST_ST << 22 | MO_8 << 30,
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@ -372,6 +374,7 @@ typedef enum {
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I3510_EON = 0x4a200000,
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I3510_ANDS = 0x6a000000,
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NOP = 0xd503201f,
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/* System instructions. */
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DMB_ISH = 0xd50338bf,
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DMB_LD = 0x00000100,
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@ -388,6 +391,11 @@ static inline uint32_t tcg_in32(TCGContext *s)
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#define tcg_out_insn(S, FMT, OP, ...) \
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glue(tcg_out_insn_,FMT)(S, glue(glue(glue(I,FMT),_),OP), ## __VA_ARGS__)
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static void tcg_out_insn_3305(TCGContext *s, AArch64Insn insn, int imm19, TCGReg rt)
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{
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tcg_out32(s, insn | (imm19 & 0x7ffff) << 5 | rt);
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}
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static void tcg_out_insn_3201(TCGContext *s, AArch64Insn insn, TCGType ext,
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TCGReg rt, int imm19)
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{
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@ -819,6 +827,17 @@ static inline void tcg_out_goto(TCGContext *s, tcg_insn_unit *target)
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tcg_out_insn(s, 3206, B, offset);
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}
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static inline void tcg_out_goto_long(TCGContext *s, tcg_insn_unit *target)
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{
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ptrdiff_t offset = target - s->code_ptr;
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if (offset == sextract64(offset, 0, 26)) {
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tcg_out_insn(s, 3206, BL, offset);
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} else {
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tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_TMP, (intptr_t)target);
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tcg_out_insn(s, 3207, BR, TCG_REG_TMP);
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}
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}
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static inline void tcg_out_goto_noaddr(TCGContext *s)
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{
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/* We pay attention here to not modify the branch target by reading from
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@ -852,15 +871,35 @@ static inline void tcg_out_call(TCGContext *s, tcg_insn_unit *target)
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}
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}
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#ifdef USE_DIRECT_JUMP
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void aarch64_tb_set_jmp_target(uintptr_t jmp_addr, uintptr_t addr)
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{
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tcg_insn_unit *code_ptr = (tcg_insn_unit *)jmp_addr;
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tcg_insn_unit *target = (tcg_insn_unit *)addr;
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tcg_insn_unit i1, i2;
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TCGType rt = TCG_TYPE_I64;
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TCGReg rd = TCG_REG_TMP;
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uint64_t pair;
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reloc_pc26_atomic(code_ptr, target);
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flush_icache_range(jmp_addr, jmp_addr + 4);
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ptrdiff_t offset = addr - jmp_addr;
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if (offset == sextract64(offset, 0, 26)) {
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i1 = I3206_B | ((offset >> 2) & 0x3ffffff);
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i2 = NOP;
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} else {
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offset = (addr >> 12) - (jmp_addr >> 12);
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/* patch ADRP */
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i1 = I3406_ADRP | (offset & 3) << 29 | (offset & 0x1ffffc) << (5 - 2) | rd;
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/* patch ADDI */
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i2 = I3401_ADDI | rt << 31 | (addr & 0xfff) << 10 | rd << 5 | rd;
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}
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pair = (uint64_t)i2 << 32 | i1;
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atomic_set((uint64_t *)jmp_addr, pair);
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flush_icache_range(jmp_addr, jmp_addr + 8);
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}
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#endif
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static inline void tcg_out_goto_label(TCGContext *s, TCGLabel *l)
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{
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if (!l->has_value) {
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@ -1364,23 +1403,33 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
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case INDEX_op_exit_tb:
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/* Reuse the zeroing that exists for goto_ptr. */
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if (a0 == 0) {
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tcg_out_goto(s, s->code_gen_epilogue);
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tcg_out_goto_long(s, s->code_gen_epilogue);
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} else {
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tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_X0, a0);
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tcg_out_goto(s, tb_ret_addr);
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tcg_out_goto_long(s, tb_ret_addr);
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}
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break;
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case INDEX_op_goto_tb:
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#ifndef USE_DIRECT_JUMP
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#error "USE_DIRECT_JUMP required for aarch64"
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#endif
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/* consistency for USE_DIRECT_JUMP */
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tcg_debug_assert(s->tb_jmp_insn_offset != NULL);
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s->tb_jmp_insn_offset[a0] = tcg_current_code_size(s);
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/* actual branch destination will be patched by
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aarch64_tb_set_jmp_target later, beware retranslation. */
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tcg_out_goto_noaddr(s);
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if (s->tb_jmp_insn_offset != NULL) {
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/* USE_DIRECT_JUMP */
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/* Ensure that ADRP+ADD are 8-byte aligned so that an atomic
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write can be used to patch the target address. */
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if ((uintptr_t)s->code_ptr & 7) {
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tcg_out32(s, NOP);
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}
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s->tb_jmp_insn_offset[a0] = tcg_current_code_size(s);
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/* actual branch destination will be patched by
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aarch64_tb_set_jmp_target later. */
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tcg_out_insn(s, 3406, ADRP, TCG_REG_TMP, 0);
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tcg_out_insn(s, 3401, ADDI, TCG_TYPE_I64, TCG_REG_TMP, TCG_REG_TMP, 0);
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} else {
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/* !USE_DIRECT_JUMP */
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tcg_debug_assert(s->tb_jmp_target_addr != NULL);
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intptr_t offset = tcg_pcrel_diff(s, (s->tb_jmp_target_addr + a0)) >> 2;
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tcg_out_insn(s, 3305, LDR, offset, TCG_REG_TMP);
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}
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tcg_out_insn(s, 3207, BR, TCG_REG_TMP);
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s->tb_jmp_reset_offset[a0] = tcg_current_code_size(s);
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break;
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@ -1547,8 +1547,8 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is_64)
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} else if (guest_base == (int16_t)guest_base) {
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tcg_out_opc_imm(s, ALIAS_PADDI, base, addr_regl, guest_base);
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} else {
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tcg_out_movi(s, TCG_TYPE_PTR, base, guest_base);
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tcg_out_opc_reg(s, ALIAS_PADD, base, base, addr_regl);
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tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP0, guest_base);
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tcg_out_opc_reg(s, ALIAS_PADD, base, TCG_TMP0, addr_regl);
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}
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tcg_out_qemu_ld_direct(s, data_regl, data_regh, base, opc, is_64);
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#endif
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} else if (guest_base == (int16_t)guest_base) {
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tcg_out_opc_imm(s, ALIAS_PADDI, base, addr_regl, guest_base);
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} else {
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tcg_out_movi(s, TCG_TYPE_PTR, base, guest_base);
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tcg_out_opc_reg(s, ALIAS_PADD, base, base, addr_regl);
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tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP0, guest_base);
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tcg_out_opc_reg(s, ALIAS_PADD, base, TCG_TMP0, addr_regl);
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}
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tcg_out_qemu_st_direct(s, data_regl, data_regh, base, opc);
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#endif
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@ -112,7 +112,7 @@ static void sys_cache_info(int *isize, int *dsize)
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static void arch_cache_info(int *isize, int *dsize)
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{
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if (*isize == 0 || *dsize == 0) {
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unsigned ctr;
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unsigned long ctr;
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/* The real cache geometry is in CCSIDR_EL1/CLIDR_EL1/CSSELR_EL1,
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but (at least under Linux) these are marked protected by the
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