sparc32 protect read-only bits in DMA CSR registers
On a real hardware changing read-only bits has no effect Use a mask common for SCSI and Ethernet registers. The crucial bit is DMA_INTR, because setting or clearing it may produce spurious interrupts. This patch allows booting Solaris 2.3 Signed-off-by: Artyom Tarasenko <atar4qemu@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
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@ -62,6 +62,9 @@
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#define DMA_DRAIN_FIFO 0x40
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#define DMA_DRAIN_FIFO 0x40
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#define DMA_RESET 0x80
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#define DMA_RESET 0x80
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/* XXX SCSI and ethernet should have different read-only bit masks */
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#define DMA_CSR_RO_MASK 0xfe000007
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typedef struct DMAState DMAState;
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typedef struct DMAState DMAState;
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struct DMAState {
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struct DMAState {
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@ -187,7 +190,7 @@ static void dma_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
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switch (saddr) {
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switch (saddr) {
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case 0:
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case 0:
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if (val & DMA_INTREN) {
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if (val & DMA_INTREN) {
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if (val & DMA_INTR) {
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if (s->dmaregs[0] & DMA_INTR) {
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DPRINTF("Raise IRQ\n");
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DPRINTF("Raise IRQ\n");
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qemu_irq_raise(s->irq);
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qemu_irq_raise(s->irq);
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}
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}
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@ -204,16 +207,17 @@ static void dma_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
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val &= ~DMA_DRAIN_FIFO;
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val &= ~DMA_DRAIN_FIFO;
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} else if (val == 0)
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} else if (val == 0)
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val = DMA_DRAIN_FIFO;
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val = DMA_DRAIN_FIFO;
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val &= 0x0fffffff;
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val &= ~DMA_CSR_RO_MASK;
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val |= DMA_VER;
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val |= DMA_VER;
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s->dmaregs[0] = (s->dmaregs[0] & DMA_CSR_RO_MASK) | val;
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break;
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break;
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case 1:
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case 1:
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s->dmaregs[0] |= DMA_LOADED;
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s->dmaregs[0] |= DMA_LOADED;
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break;
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/* fall through */
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default:
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default:
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s->dmaregs[saddr] = val;
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break;
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break;
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}
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}
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s->dmaregs[saddr] = val;
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}
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}
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static CPUReadMemoryFunc * const dma_mem_read[3] = {
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static CPUReadMemoryFunc * const dma_mem_read[3] = {
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