PowerPC SPE extension fix: must always preserve GPR high bits when
running in 32 bits mode. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3631 c046a42c-6fe2-441c-8c8c-71466251a162
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@ -530,7 +530,7 @@ struct CPUPPCState {
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/* general purpose registers */
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/* general purpose registers */
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ppc_gpr_t gpr[32];
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ppc_gpr_t gpr[32];
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#if TARGET_GPR_BITS < 64
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#if !defined(TARGET_PPC64)
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/* Storage for GPR MSB, used by the SPE extension */
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/* Storage for GPR MSB, used by the SPE extension */
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ppc_gpr_t gprh[32];
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ppc_gpr_t gprh[32];
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#endif
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#endif
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@ -58,7 +58,7 @@ void OPPROTO glue(op_store_T2_gpr_gpr, REG) (void)
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#endif
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#endif
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/* General purpose registers containing vector operands moves */
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/* General purpose registers containing vector operands moves */
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#if TARGET_GPR_BITS < 64
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#if !defined(TARGET_PPC64)
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void OPPROTO glue(op_load_gpr64_T0_gpr, REG) (void)
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void OPPROTO glue(op_load_gpr64_T0_gpr, REG) (void)
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{
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{
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T0_64 = (uint64_t)env->gpr[REG] | ((uint64_t)env->gprh[REG] << 32);
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T0_64 = (uint64_t)env->gpr[REG] | ((uint64_t)env->gprh[REG] << 32);
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@ -101,7 +101,7 @@ void OPPROTO glue(op_store_T2_gpr64_gpr, REG) (void)
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RETURN();
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RETURN();
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}
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}
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#endif
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#endif
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#endif /* TARGET_GPR_BITS < 64 */
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#endif /* !defined(TARGET_PPC64) */
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/* Altivec registers moves */
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/* Altivec registers moves */
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void OPPROTO glue(op_load_avr_A0_avr, REG) (void)
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void OPPROTO glue(op_load_avr_A0_avr, REG) (void)
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@ -5822,7 +5822,7 @@ GEN_VR_STX(vxl, 0x07, 0x0F);
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/*** SPE extension ***/
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/*** SPE extension ***/
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/* Register moves */
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/* Register moves */
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#if TARGET_GPR_BITS < 64
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#if !defined(TARGET_PPC64)
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GEN32(gen_op_load_gpr64_T0, gen_op_load_gpr64_T0_gpr);
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GEN32(gen_op_load_gpr64_T0, gen_op_load_gpr64_T0_gpr);
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GEN32(gen_op_load_gpr64_T1, gen_op_load_gpr64_T1_gpr);
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GEN32(gen_op_load_gpr64_T1, gen_op_load_gpr64_T1_gpr);
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@ -5836,7 +5836,7 @@ GEN32(gen_op_store_T1_gpr64, gen_op_store_T1_gpr64_gpr);
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GEN32(gen_op_store_T2_gpr64, gen_op_store_T2_gpr64_gpr);
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GEN32(gen_op_store_T2_gpr64, gen_op_store_T2_gpr64_gpr);
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#endif
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#endif
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#else /* TARGET_GPR_BITS < 64 */
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#else /* !defined(TARGET_PPC64) */
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/* No specific load/store functions: GPRs are already 64 bits */
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/* No specific load/store functions: GPRs are already 64 bits */
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#define gen_op_load_gpr64_T0 gen_op_load_gpr_T0
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#define gen_op_load_gpr64_T0 gen_op_load_gpr_T0
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@ -5851,7 +5851,7 @@ GEN32(gen_op_store_T2_gpr64, gen_op_store_T2_gpr64_gpr);
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#define gen_op_store_T2_gpr64 gen_op_store_T2_gpr
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#define gen_op_store_T2_gpr64 gen_op_store_T2_gpr
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#endif
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#endif
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#endif /* TARGET_GPR_BITS < 64 */
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#endif /* !defined(TARGET_PPC64) */
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#define GEN_SPE(name0, name1, opc2, opc3, inval, type) \
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#define GEN_SPE(name0, name1, opc2, opc3, inval, type) \
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GEN_HANDLER(name0##_##name1, 0x04, opc2, opc3, inval, type) \
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GEN_HANDLER(name0##_##name1, 0x04, opc2, opc3, inval, type) \
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