USB OHCI: add support for big endian targets
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6368 c046a42c-6fe2-441c-8c8c-71466251a162
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aurel32
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470d86b736
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65e1d81b29
198
hw/usb-ohci.c
198
hw/usb-ohci.c
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@ -1360,103 +1360,135 @@ static void ohci_port_set_status(OHCIState *ohci, int portnum, uint32_t val)
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static uint32_t ohci_mem_read(void *ptr, target_phys_addr_t addr)
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{
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OHCIState *ohci = ptr;
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uint32_t retval;
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/* Only aligned reads are allowed on OHCI */
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if (addr & 3) {
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fprintf(stderr, "usb-ohci: Mis-aligned read\n");
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return 0xffffffff;
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}
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if (addr >= 0x54 && addr < 0x54 + ohci->num_ports * 4) {
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} else if (addr >= 0x54 && addr < 0x54 + ohci->num_ports * 4) {
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/* HcRhPortStatus */
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return ohci->rhport[(addr - 0x54) >> 2].ctrl | OHCI_PORT_PPS;
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retval = ohci->rhport[(addr - 0x54) >> 2].ctrl | OHCI_PORT_PPS;
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} else {
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switch (addr >> 2) {
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case 0: /* HcRevision */
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retval = 0x10;
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break;
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case 1: /* HcControl */
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retval = ohci->ctl;
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break;
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case 2: /* HcCommandStatus */
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retval = ohci->status;
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break;
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case 3: /* HcInterruptStatus */
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retval = ohci->intr_status;
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break;
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case 4: /* HcInterruptEnable */
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case 5: /* HcInterruptDisable */
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retval = ohci->intr;
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break;
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case 6: /* HcHCCA */
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retval = ohci->hcca;
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break;
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case 7: /* HcPeriodCurrentED */
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retval = ohci->per_cur;
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break;
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case 8: /* HcControlHeadED */
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retval = ohci->ctrl_head;
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break;
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case 9: /* HcControlCurrentED */
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retval = ohci->ctrl_cur;
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break;
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case 10: /* HcBulkHeadED */
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retval = ohci->bulk_head;
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break;
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case 11: /* HcBulkCurrentED */
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retval = ohci->bulk_cur;
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break;
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case 12: /* HcDoneHead */
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retval = ohci->done;
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break;
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case 13: /* HcFmInterretval */
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retval = (ohci->fit << 31) | (ohci->fsmps << 16) | (ohci->fi);
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break;
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case 14: /* HcFmRemaining */
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retval = ohci_get_frame_remaining(ohci);
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break;
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case 15: /* HcFmNumber */
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retval = ohci->frame_number;
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break;
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case 16: /* HcPeriodicStart */
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retval = ohci->pstart;
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break;
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case 17: /* HcLSThreshold */
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retval = ohci->lst;
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break;
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case 18: /* HcRhDescriptorA */
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retval = ohci->rhdesc_a;
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break;
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case 19: /* HcRhDescriptorB */
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retval = ohci->rhdesc_b;
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break;
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case 20: /* HcRhStatus */
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retval = ohci->rhstatus;
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break;
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/* PXA27x specific registers */
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case 24: /* HcStatus */
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retval = ohci->hstatus & ohci->hmask;
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break;
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case 25: /* HcHReset */
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retval = ohci->hreset;
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break;
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case 26: /* HcHInterruptEnable */
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retval = ohci->hmask;
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break;
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case 27: /* HcHInterruptTest */
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retval = ohci->htest;
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break;
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default:
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fprintf(stderr, "ohci_read: Bad offset %x\n", (int)addr);
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retval = 0xffffffff;
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}
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}
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switch (addr >> 2) {
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case 0: /* HcRevision */
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return 0x10;
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case 1: /* HcControl */
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return ohci->ctl;
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case 2: /* HcCommandStatus */
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return ohci->status;
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case 3: /* HcInterruptStatus */
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return ohci->intr_status;
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case 4: /* HcInterruptEnable */
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case 5: /* HcInterruptDisable */
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return ohci->intr;
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case 6: /* HcHCCA */
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return ohci->hcca;
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case 7: /* HcPeriodCurrentED */
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return ohci->per_cur;
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case 8: /* HcControlHeadED */
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return ohci->ctrl_head;
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case 9: /* HcControlCurrentED */
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return ohci->ctrl_cur;
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case 10: /* HcBulkHeadED */
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return ohci->bulk_head;
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case 11: /* HcBulkCurrentED */
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return ohci->bulk_cur;
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case 12: /* HcDoneHead */
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return ohci->done;
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case 13: /* HcFmInterval */
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return (ohci->fit << 31) | (ohci->fsmps << 16) | (ohci->fi);
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case 14: /* HcFmRemaining */
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return ohci_get_frame_remaining(ohci);
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case 15: /* HcFmNumber */
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return ohci->frame_number;
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case 16: /* HcPeriodicStart */
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return ohci->pstart;
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case 17: /* HcLSThreshold */
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return ohci->lst;
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case 18: /* HcRhDescriptorA */
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return ohci->rhdesc_a;
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case 19: /* HcRhDescriptorB */
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return ohci->rhdesc_b;
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case 20: /* HcRhStatus */
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return ohci->rhstatus;
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/* PXA27x specific registers */
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case 24: /* HcStatus */
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return ohci->hstatus & ohci->hmask;
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case 25: /* HcHReset */
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return ohci->hreset;
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case 26: /* HcHInterruptEnable */
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return ohci->hmask;
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case 27: /* HcHInterruptTest */
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return ohci->htest;
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default:
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fprintf(stderr, "ohci_read: Bad offset %x\n", (int)addr);
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return 0xffffffff;
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}
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#ifdef TARGET_WORDS_BIGENDIAN
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retval = bswap32(retval);
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#endif
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return retval;
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}
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static void ohci_mem_write(void *ptr, target_phys_addr_t addr, uint32_t val)
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{
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OHCIState *ohci = ptr;
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#ifdef TARGET_WORDS_BIGENDIAN
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val = bswap32(val);
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#endif
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/* Only aligned reads are allowed on OHCI */
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if (addr & 3) {
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fprintf(stderr, "usb-ohci: Mis-aligned write\n");
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