target/arm: Add assertion about FSC format for syndrome registers
In tlb_fill() we construct a syndrome register value from a fault status register value which is filled in by arm_tlb_fill(). arm_tlb_fill() returns FSR values which might be in the format used with short-format page descriptors, or the format used with long-format (LPAE) descriptors. The syndrome register always uses LPAE-format FSR status codes. It isn't actually possible to end up delivering a syndrome register value to the guest for a fault which is reported with a short-format FSR (that kind of stage 1 fault will only happen for an AArch32 translation regime which doesn't have a syndrome register, and can never be redirected to an AArch64 or Hyp exception level). Add an assertion which checks this, and adjust the code so that we construct a syndrome with an invalid status code, rather than allowing set bits in the FSR input to randomly corrupt other fields in the syndrome. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1491486152-24304-1-git-send-email-peter.maydell@linaro.org
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@ -130,7 +130,7 @@ void tlb_fill(CPUState *cs, target_ulong addr, MMUAccessType access_type,
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if (unlikely(ret)) {
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ARMCPU *cpu = ARM_CPU(cs);
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CPUARMState *env = &cpu->env;
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uint32_t syn, exc;
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uint32_t syn, exc, fsc;
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unsigned int target_el;
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bool same_el;
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@ -145,19 +145,32 @@ void tlb_fill(CPUState *cs, target_ulong addr, MMUAccessType access_type,
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env->cp15.hpfar_el2 = extract64(fi.s2addr, 12, 47) << 4;
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}
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same_el = arm_current_el(env) == target_el;
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/* AArch64 syndrome does not have an LPAE bit */
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syn = fsr & ~(1 << 9);
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if (fsr & (1 << 9)) {
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/* LPAE format fault status register : bottom 6 bits are
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* status code in the same form as needed for syndrome
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*/
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fsc = extract32(fsr, 0, 6);
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} else {
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/* Short format FSR : this fault will never actually be reported
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* to an EL that uses a syndrome register. Check that here,
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* and use a (currently) reserved FSR code in case the constructed
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* syndrome does leak into the guest somehow.
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*/
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assert(target_el != 2 && !arm_el_is_aa64(env, target_el));
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fsc = 0x3f;
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}
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/* For insn and data aborts we assume there is no instruction syndrome
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* information; this is always true for exceptions reported to EL1.
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*/
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if (access_type == MMU_INST_FETCH) {
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syn = syn_insn_abort(same_el, 0, fi.s1ptw, syn);
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syn = syn_insn_abort(same_el, 0, fi.s1ptw, fsc);
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exc = EXCP_PREFETCH_ABORT;
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} else {
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syn = merge_syn_data_abort(env->exception.syndrome, target_el,
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same_el, fi.s1ptw,
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access_type == MMU_DATA_STORE, syn);
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access_type == MMU_DATA_STORE, fsc);
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if (access_type == MMU_DATA_STORE
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&& arm_feature(env, ARM_FEATURE_V6)) {
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fsr |= (1 << 11);
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