PIIX ELCR register support
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@820 c046a42c-6fe2-441c-8c8c-71466251a162
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69135b5c04
commit
660de33686
51
hw/i8259.c
51
hw/i8259.c
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@ -43,6 +43,8 @@ typedef struct PicState {
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uint8_t rotate_on_auto_eoi;
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uint8_t special_fully_nested_mode;
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uint8_t init4; /* true if 4 byte init */
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uint8_t elcr; /* PIIX edge/trigger selection*/
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uint8_t elcr_mask;
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} PicState;
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/* 0 is master pic, 1 is slave pic */
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@ -54,6 +56,17 @@ static inline void pic_set_irq1(PicState *s, int irq, int level)
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{
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int mask;
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mask = 1 << irq;
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if (s->elcr & mask) {
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/* level triggered */
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if (level) {
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s->irr |= mask;
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s->last_irr |= mask;
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} else {
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s->irr &= ~mask;
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s->last_irr &= ~mask;
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}
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} else {
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/* edge triggered */
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if (level) {
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if ((s->last_irr & mask) == 0)
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s->irr |= mask;
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@ -61,6 +74,7 @@ static inline void pic_set_irq1(PicState *s, int irq, int level)
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} else {
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s->last_irr &= ~mask;
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}
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}
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}
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/* return the highest priority found in mask (highest = smallest
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@ -205,7 +219,7 @@ int cpu_get_pic_interrupt(CPUState *env)
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static void pic_ioport_write(void *opaque, uint32_t addr, uint32_t val)
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{
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PicState *s = opaque;
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int priority, cmd, irq;
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int priority, cmd, irq, tmp;
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#ifdef DEBUG_PIC
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printf("pic_write: addr=0x%02x val=0x%02x\n", addr, val);
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@ -214,7 +228,10 @@ static void pic_ioport_write(void *opaque, uint32_t addr, uint32_t val)
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if (addr == 0) {
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if (val & 0x10) {
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/* init */
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tmp = s->elcr_mask;
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memset(s, 0, sizeof(PicState));
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s->elcr_mask = tmp;
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s->init_state = 1;
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s->init4 = val & 1;
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if (val & 0x02)
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@ -356,6 +373,18 @@ uint32_t pic_intack_read(CPUState *env)
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return ret;
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}
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static void elcr_ioport_write(void *opaque, uint32_t addr, uint32_t val)
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{
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PicState *s = opaque;
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s->elcr = val & s->elcr_mask;
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}
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static uint32_t elcr_ioport_read(void *opaque, uint32_t addr1)
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{
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PicState *s = opaque;
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return s->elcr;
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}
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static void pic_save(QEMUFile *f, void *opaque)
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{
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PicState *s = opaque;
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@ -374,6 +403,7 @@ static void pic_save(QEMUFile *f, void *opaque)
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qemu_put_8s(f, &s->rotate_on_auto_eoi);
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qemu_put_8s(f, &s->special_fully_nested_mode);
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qemu_put_8s(f, &s->init4);
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qemu_put_8s(f, &s->elcr);
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}
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static int pic_load(QEMUFile *f, void *opaque, int version_id)
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@ -397,15 +427,19 @@ static int pic_load(QEMUFile *f, void *opaque, int version_id)
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qemu_get_8s(f, &s->rotate_on_auto_eoi);
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qemu_get_8s(f, &s->special_fully_nested_mode);
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qemu_get_8s(f, &s->init4);
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qemu_get_8s(f, &s->elcr);
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return 0;
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}
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/* XXX: add generic master/slave system */
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static void pic_init1(int io_addr, PicState *s)
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static void pic_init1(int io_addr, int elcr_addr, PicState *s)
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{
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register_ioport_write(io_addr, 2, 1, pic_ioport_write, s);
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register_ioport_read(io_addr, 2, 1, pic_ioport_read, s);
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if (elcr_addr >= 0) {
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register_ioport_write(elcr_addr, 1, 1, elcr_ioport_write, s);
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register_ioport_read(elcr_addr, 1, 1, elcr_ioport_read, s);
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}
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register_savevm("i8259", io_addr, 1, pic_save, pic_load, s);
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}
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@ -416,15 +450,18 @@ void pic_info(void)
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for(i=0;i<2;i++) {
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s = &pics[i];
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term_printf("pic%d: irr=%02x imr=%02x isr=%02x hprio=%d irq_base=%02x rr_sel=%d\n",
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i, s->irr, s->imr, s->isr, s->priority_add, s->irq_base, s->read_reg_select);
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term_printf("pic%d: irr=%02x imr=%02x isr=%02x hprio=%d irq_base=%02x rr_sel=%d elcr=%02x\n",
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i, s->irr, s->imr, s->isr, s->priority_add,
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s->irq_base, s->read_reg_select, s->elcr);
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}
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}
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void pic_init(void)
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{
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pic_init1(0x20, &pics[0]);
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pic_init1(0xa0, &pics[1]);
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pic_init1(0x20, 0x4d0, &pics[0]);
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pic_init1(0xa0, 0x4d1, &pics[1]);
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pics[0].elcr_mask = 0xf8;
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pics[1].elcr_mask = 0xde;
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}
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