target/arm: Add MMU indexes for secure v8M
Now that MPU lookups can return different results for v8M when the CPU is in secure vs non-secure state, we need to have separate MMU indexes; add the secure counterparts to the existing three M profile MMU indexes. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 1503414539-28762-6-git-send-email-peter.maydell@linaro.org
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@ -2103,6 +2103,10 @@ static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx,
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* Execution priority negative (this is like privileged, but the
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* MPU HFNMIENA bit means that it may have different access permission
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* check results to normal privileged code, so can't share a TLB).
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* If the CPU supports the v8M Security Extension then there are also:
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* Secure User
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* Secure Privileged
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* Secure, execution priority negative
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*
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* The ARMMMUIdx and the mmu index value used by the core QEMU TLB code
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* are not quite the same -- different CPU types (most notably M profile
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@ -2140,6 +2144,9 @@ typedef enum ARMMMUIdx {
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ARMMMUIdx_MUser = 0 | ARM_MMU_IDX_M,
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ARMMMUIdx_MPriv = 1 | ARM_MMU_IDX_M,
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ARMMMUIdx_MNegPri = 2 | ARM_MMU_IDX_M,
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ARMMMUIdx_MSUser = 3 | ARM_MMU_IDX_M,
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ARMMMUIdx_MSPriv = 4 | ARM_MMU_IDX_M,
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ARMMMUIdx_MSNegPri = 5 | ARM_MMU_IDX_M,
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/* Indexes below here don't have TLBs and are used only for AT system
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* instructions or for the first stage of an S12 page table walk.
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*/
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@ -2161,6 +2168,9 @@ typedef enum ARMMMUIdxBit {
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ARMMMUIdxBit_MUser = 1 << 0,
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ARMMMUIdxBit_MPriv = 1 << 1,
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ARMMMUIdxBit_MNegPri = 1 << 2,
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ARMMMUIdxBit_MSUser = 1 << 3,
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ARMMMUIdxBit_MSPriv = 1 << 4,
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ARMMMUIdxBit_MSNegPri = 1 << 5,
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} ARMMMUIdxBit;
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#define MMU_USER_IDX 0
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@ -2186,7 +2196,8 @@ static inline int arm_mmu_idx_to_el(ARMMMUIdx mmu_idx)
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case ARM_MMU_IDX_A:
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return mmu_idx & 3;
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case ARM_MMU_IDX_M:
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return mmu_idx == ARMMMUIdx_MUser ? 0 : 1;
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return (mmu_idx == ARMMMUIdx_MUser || mmu_idx == ARMMMUIdx_MSUser)
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? 0 : 1;
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default:
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g_assert_not_reached();
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}
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@ -2205,7 +2216,11 @@ static inline int cpu_mmu_index(CPUARMState *env, bool ifetch)
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*/
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if ((env->v7m.exception > 0 && env->v7m.exception <= 3)
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|| env->v7m.faultmask) {
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return arm_to_core_mmu_idx(ARMMMUIdx_MNegPri);
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mmu_idx = ARMMMUIdx_MNegPri;
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}
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if (env->v7m.secure) {
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mmu_idx += ARMMMUIdx_MSUser;
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}
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return arm_to_core_mmu_idx(mmu_idx);
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@ -7032,6 +7032,9 @@ static inline uint32_t regime_el(CPUARMState *env, ARMMMUIdx mmu_idx)
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case ARMMMUIdx_MPriv:
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case ARMMMUIdx_MNegPri:
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case ARMMMUIdx_MUser:
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case ARMMMUIdx_MSPriv:
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case ARMMMUIdx_MSNegPri:
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case ARMMMUIdx_MSUser:
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return 1;
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default:
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g_assert_not_reached();
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@ -7055,6 +7058,9 @@ static inline bool regime_is_secure(CPUARMState *env, ARMMMUIdx mmu_idx)
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case ARMMMUIdx_S1E3:
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case ARMMMUIdx_S1SE0:
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case ARMMMUIdx_S1SE1:
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case ARMMMUIdx_MSPriv:
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case ARMMMUIdx_MSNegPri:
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case ARMMMUIdx_MSUser:
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return true;
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default:
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g_assert_not_reached();
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@ -7076,7 +7082,8 @@ static inline bool regime_translation_disabled(CPUARMState *env,
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(R_V7M_MPU_CTRL_ENABLE_MASK | R_V7M_MPU_CTRL_HFNMIENA_MASK)) {
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case R_V7M_MPU_CTRL_ENABLE_MASK:
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/* Enabled, but not for HardFault and NMI */
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return mmu_idx == ARMMMUIdx_MNegPri;
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return mmu_idx == ARMMMUIdx_MNegPri ||
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mmu_idx == ARMMMUIdx_MSNegPri;
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case R_V7M_MPU_CTRL_ENABLE_MASK | R_V7M_MPU_CTRL_HFNMIENA_MASK:
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/* Enabled for all cases */
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return false;
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