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q35: add test for SMRAM.D_LCK

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Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Acked-by: Michael S. Tsirkin <mst@redhat.com>
[Fix compilation of the newly introduced test. - Paolo]
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
This commit is contained in:
Gerd Hoffmann 2015-04-14 15:11:36 +02:00 committed by Paolo Bonzini
parent 68c77acfb1
commit 66e2ec2417
2 changed files with 94 additions and 0 deletions
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3
tests/Makefile
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@ -174,6 +174,8 @@ gcov-files-i386-y += hw/usb/dev-storage.c
check-qtest-i386-y += tests/usb-hcd-xhci-test$(EXESUF)
gcov-files-i386-y += hw/usb/hcd-xhci.c
check-qtest-i386-y += tests/pc-cpu-test$(EXESUF)
check-qtest-i386-y += tests/q35-test$(EXESUF)
gcov-files-i386-y += hw/pci-host/q35.c
check-qtest-i386-$(CONFIG_LINUX) += tests/vhost-user-test$(EXESUF)
check-qtest-x86_64-y = $(check-qtest-i386-y)
gcov-files-i386-y += i386-softmmu/hw/timer/mc146818rtc.c
@ -355,6 +357,7 @@ tests/boot-order-test$(EXESUF): tests/boot-order-test.o $(libqos-obj-y)
tests/bios-tables-test$(EXESUF): tests/bios-tables-test.o $(libqos-obj-y)
tests/tmp105-test$(EXESUF): tests/tmp105-test.o $(libqos-omap-obj-y)
tests/i440fx-test$(EXESUF): tests/i440fx-test.o $(libqos-pc-obj-y)
tests/q35-test$(EXESUF): tests/q35-test.o $(libqos-pc-obj-y)
tests/fw_cfg-test$(EXESUF): tests/fw_cfg-test.o $(libqos-pc-obj-y)
tests/e1000-test$(EXESUF): tests/e1000-test.o
tests/rtl8139-test$(EXESUF): tests/rtl8139-test.o $(libqos-pc-obj-y)

91
tests/q35-test.c Normal file
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@ -0,0 +1,91 @@
/*
* QTest testcase for Q35 northbridge
*
* Copyright (c) 2015 Red Hat, Inc.
*
* Author: Gerd Hoffmann <kraxel@redhat.com>
*
* This work is licensed under the terms of the GNU GPL, version 2 or later.
* See the COPYING file in the top-level directory.
*/
#include <glib.h>
#include <string.h>
#include "libqtest.h"
#include "libqos/pci.h"
#include "libqos/pci-pc.h"
#include "qemu/osdep.h"
#include "hw/pci-host/q35.h"
static void smram_set_bit(QPCIDevice *pcidev, uint8_t mask, bool enabled)
{
uint8_t smram;
smram = qpci_config_readb(pcidev, MCH_HOST_BRIDGE_SMRAM);
if (enabled) {
smram |= mask;
} else {
smram &= ~mask;
}
qpci_config_writeb(pcidev, MCH_HOST_BRIDGE_SMRAM, smram);
}
static bool smram_test_bit(QPCIDevice *pcidev, uint8_t mask)
{
uint8_t smram;
smram = qpci_config_readb(pcidev, MCH_HOST_BRIDGE_SMRAM);
return smram & mask;
}
static void test_smram_lock(void)
{
QPCIBus *pcibus;
QPCIDevice *pcidev;
QDict *response;
pcibus = qpci_init_pc();
g_assert(pcibus != NULL);
pcidev = qpci_device_find(pcibus, 0);
g_assert(pcidev != NULL);
/* check open is settable */
smram_set_bit(pcidev, MCH_HOST_BRIDGE_SMRAM_D_OPEN, false);
g_assert(smram_test_bit(pcidev, MCH_HOST_BRIDGE_SMRAM_D_OPEN) == false);
smram_set_bit(pcidev, MCH_HOST_BRIDGE_SMRAM_D_OPEN, true);
g_assert(smram_test_bit(pcidev, MCH_HOST_BRIDGE_SMRAM_D_OPEN) == true);
/* lock, check open is cleared & not settable */
smram_set_bit(pcidev, MCH_HOST_BRIDGE_SMRAM_D_LCK, true);
g_assert(smram_test_bit(pcidev, MCH_HOST_BRIDGE_SMRAM_D_OPEN) == false);
smram_set_bit(pcidev, MCH_HOST_BRIDGE_SMRAM_D_OPEN, true);
g_assert(smram_test_bit(pcidev, MCH_HOST_BRIDGE_SMRAM_D_OPEN) == false);
/* reset */
response = qmp("{'execute': 'system_reset', 'arguments': {} }");
g_assert(response);
g_assert(!qdict_haskey(response, "error"));
QDECREF(response);
/* check open is settable again */
smram_set_bit(pcidev, MCH_HOST_BRIDGE_SMRAM_D_OPEN, false);
g_assert(smram_test_bit(pcidev, MCH_HOST_BRIDGE_SMRAM_D_OPEN) == false);
smram_set_bit(pcidev, MCH_HOST_BRIDGE_SMRAM_D_OPEN, true);
g_assert(smram_test_bit(pcidev, MCH_HOST_BRIDGE_SMRAM_D_OPEN) == true);
}
int main(int argc, char **argv)
{
int ret;
g_test_init(&argc, &argv, NULL);
qtest_add_func("/q35/smram/lock", test_smram_lock);
qtest_start("-M q35");
ret = g_test_run();
qtest_end();
return ret;
}