RISC-V: Clear mtval/stval on exceptions without info
mtval/stval must be set on all exceptions but zero is a legal value if there is no exception specific info. Placing the instruction bytes for illegal instruction exceptions in mtval/stval is an optional feature and is currently not supported by QEMU RISC-V. Cc: Sagar Karandikar <sagark@eecs.berkeley.edu> Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Cc: Palmer Dabbelt <palmer@sifive.com> Cc: Alistair Francis <Alistair.Francis@wdc.com> Signed-off-by: Michael Clark <mjc@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
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@ -466,6 +466,10 @@ void riscv_cpu_do_interrupt(CPUState *cs)
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": badaddr 0x" TARGET_FMT_lx, env->mhartid, env->badaddr);
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}
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env->sbadaddr = env->badaddr;
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} else {
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/* otherwise we must clear sbadaddr/stval
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* todo: support populating stval on illegal instructions */
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env->sbadaddr = 0;
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}
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target_ulong s = env->mstatus;
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@ -487,6 +491,10 @@ void riscv_cpu_do_interrupt(CPUState *cs)
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": badaddr 0x" TARGET_FMT_lx, env->mhartid, env->badaddr);
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}
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env->mbadaddr = env->badaddr;
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} else {
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/* otherwise we must clear mbadaddr/mtval
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* todo: support populating mtval on illegal instructions */
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env->mbadaddr = 0;
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}
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target_ulong s = env->mstatus;
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