riscv/sifive_u: Manually define the machine
Instead of using the DEFINE_MACHINE() macro to define the machine let's do it manually. This allows us to specify machine properties. This patch is no functional change. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
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@ -311,8 +311,7 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
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static void riscv_sifive_u_init(MachineState *machine)
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{
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const struct MemmapEntry *memmap = sifive_u_memmap;
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SiFiveUState *s = g_new0(SiFiveUState, 1);
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SiFiveUState *s = RISCV_U_MACHINE(machine);
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MemoryRegion *system_memory = get_system_memory();
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MemoryRegion *main_mem = g_new(MemoryRegion, 1);
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MemoryRegion *flash0 = g_new(MemoryRegion, 1);
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@ -434,6 +433,10 @@ static void riscv_sifive_u_soc_init(Object *obj)
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TYPE_CADENCE_GEM);
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}
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static void riscv_sifive_u_machine_instance_init(Object *obj)
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{
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}
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static void riscv_sifive_u_soc_realize(DeviceState *dev, Error **errp)
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{
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MachineState *ms = MACHINE(qdev_get_machine());
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@ -547,17 +550,6 @@ static void riscv_sifive_u_soc_realize(DeviceState *dev, Error **errp)
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memmap[SIFIVE_U_GEM_MGMT].base, memmap[SIFIVE_U_GEM_MGMT].size);
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}
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static void riscv_sifive_u_machine_init(MachineClass *mc)
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{
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mc->desc = "RISC-V Board compatible with SiFive U SDK";
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mc->init = riscv_sifive_u_init;
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mc->max_cpus = SIFIVE_U_MANAGEMENT_CPU_COUNT + SIFIVE_U_COMPUTE_CPU_COUNT;
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mc->min_cpus = SIFIVE_U_MANAGEMENT_CPU_COUNT + 1;
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mc->default_cpus = mc->min_cpus;
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}
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DEFINE_MACHINE("sifive_u", riscv_sifive_u_machine_init)
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static void riscv_sifive_u_soc_class_init(ObjectClass *oc, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(oc);
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@ -581,3 +573,29 @@ static void riscv_sifive_u_soc_register_types(void)
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}
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type_init(riscv_sifive_u_soc_register_types)
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static void riscv_sifive_u_machine_class_init(ObjectClass *oc, void *data)
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{
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MachineClass *mc = MACHINE_CLASS(oc);
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mc->desc = "RISC-V Board compatible with SiFive U SDK";
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mc->init = riscv_sifive_u_init;
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mc->max_cpus = SIFIVE_U_MANAGEMENT_CPU_COUNT + SIFIVE_U_COMPUTE_CPU_COUNT;
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mc->min_cpus = SIFIVE_U_MANAGEMENT_CPU_COUNT + 1;
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mc->default_cpus = mc->min_cpus;
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}
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static const TypeInfo riscv_sifive_u_machine_typeinfo = {
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.name = MACHINE_TYPE_NAME("sifive_u"),
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.parent = TYPE_MACHINE,
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.class_init = riscv_sifive_u_machine_class_init,
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.instance_init = riscv_sifive_u_machine_instance_init,
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.instance_size = sizeof(SiFiveUState),
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};
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static void riscv_sifive_u_machine_init_register_types(void)
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{
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type_register_static(&riscv_sifive_u_machine_typeinfo);
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}
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type_init(riscv_sifive_u_machine_init_register_types)
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@ -44,12 +44,17 @@ typedef struct SiFiveUSoCState {
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CadenceGEMState gem;
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} SiFiveUSoCState;
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#define TYPE_RISCV_U_MACHINE MACHINE_TYPE_NAME("sifive_u")
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#define RISCV_U_MACHINE(obj) \
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OBJECT_CHECK(SiFiveUState, (obj), TYPE_RISCV_U_MACHINE)
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typedef struct SiFiveUState {
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/*< private >*/
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SysBusDevice parent_obj;
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MachineState parent_obj;
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/*< public >*/
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SiFiveUSoCState soc;
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void *fdt;
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int fdt_size;
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} SiFiveUState;
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