From 2838b1d6356044eb240edd4e1b9b5ab5946c5b28 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Date: Wed, 5 May 2021 23:38:36 +0200 Subject: [PATCH 01/15] target/mips: Fix potential integer overflow (CID 1452921) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Use the BIT_ULL() macro to ensure we use 64-bit arithmetic. This fixes the following Coverity issue (OVERFLOW_BEFORE_WIDEN): CID 1452921: Integer handling issues: Potentially overflowing expression "1 << w" with type "int" (32 bits, signed) is evaluated using 32-bit arithmetic, and then used in a context that expects an expression of type "uint64_t" (64 bits, unsigned). Fixes: 074cfcb4dae ("target/mips: Implement hardware page table walker") Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20210505215119.1517465-1-f4bug@amsat.org> --- target/mips/tcg/sysemu/tlb_helper.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/target/mips/tcg/sysemu/tlb_helper.c b/target/mips/tcg/sysemu/tlb_helper.c index 259f780d19..a150a014ec 100644 --- a/target/mips/tcg/sysemu/tlb_helper.c +++ b/target/mips/tcg/sysemu/tlb_helper.c @@ -17,6 +17,7 @@ * License along with this library; if not, see . */ #include "qemu/osdep.h" +#include "qemu/bitops.h" #include "cpu.h" #include "internal.h" @@ -659,7 +660,7 @@ static int walk_directory(CPUMIPSState *env, uint64_t *vaddr, w = directory_index - 1; if (directory_index & 0x1) { /* Generate adjacent page from same PTE for odd TLB page */ - lsb = (1 << w) >> 6; + lsb = BIT_ULL(w) >> 6; *pw_entrylo0 = entry & ~lsb; /* even page */ *pw_entrylo1 = entry | lsb; /* odd page */ } else if (dph) { From 96342d53a881a5686b1e4797aead1c025985772e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Date: Sun, 30 May 2021 11:36:29 +0200 Subject: [PATCH 02/15] target/mips: Fix TCG temporary leaks in gen_pool32a5_nanomips_insn() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Fix a pair of TCG temporary leak when translating nanoMIPS SHILO opcode. Fixes: 3285a3e4445 ("target/mips: Add emulation of DSP ASE for nanoMIPS") Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20210530094538.1275329-1-f4bug@amsat.org> --- target/mips/tcg/translate.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c index 797eba4434..120484a6c0 100644 --- a/target/mips/tcg/translate.c +++ b/target/mips/tcg/translate.c @@ -20182,6 +20182,8 @@ static void gen_pool32a5_nanomips_insn(DisasContext *ctx, int opc, tcg_gen_movi_tl(tv0, rd >> 3); tcg_gen_movi_tl(tv1, imm); gen_helper_shilo(tv0, tv1, cpu_env); + tcg_temp_free(tv1); + tcg_temp_free(tv0); } break; case NM_MULEQ_S_W_PHL: From 6eb223104c4e5cdfeaf57cff20fb1ad54084393b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Date: Thu, 17 Jun 2021 18:03:34 +0200 Subject: [PATCH 03/15] target/mips: Fix more TCG temporary leaks in gen_pool32a5_nanomips_insn MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Fix multiple TCG temporary leaks in gen_pool32a5_nanomips_insn(). Fixes: 3285a3e4445 ("target/mips: Add emulation of DSP ASE for nanoMIPS - part 1") Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20210617174323.2900831-3-f4bug@amsat.org> --- target/mips/tcg/translate.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c index 120484a6c0..09b19262c8 100644 --- a/target/mips/tcg/translate.c +++ b/target/mips/tcg/translate.c @@ -20298,6 +20298,10 @@ static void gen_pool32a5_nanomips_insn(DisasContext *ctx, int opc, gen_reserved_instruction(ctx); break; } + + tcg_temp_free(v2_t); + tcg_temp_free(v1_t); + tcg_temp_free(t0); } static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx) From a071578b93e850dcbebbe2c0cfe86e7977ddffa7 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Date: Sat, 29 May 2021 18:08:19 +0200 Subject: [PATCH 04/15] target/mips: Raise exception when DINSV opcode used with DSP disabled MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Per the "MIPS® DSP Module for MIPS64 Architecture" manual, rev. 3.02, Table 5.3 "SPECIAL3 Encoding of Function Field for DSP Module": If the Module/ASE is not implemented, executing such an instruction must cause a Reserved Instruction Exception. The DINSV instruction lists the following exceptions: - Reserved Instruction - DSP Disabled If the MIPS core doesn't support the DSP module, or the DSP is disabled, do not handle the '$rt = $0' case as a no-op but raise the proper exception instead. Cc: Jia Liu Fixes: 1cb6686cf92 ("target-mips: Add ASE DSP bit/manipulation instructions") Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20210529165443.1114402-1-f4bug@amsat.org> --- target/mips/tcg/translate.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c index 09b19262c8..3fd0c48d77 100644 --- a/target/mips/tcg/translate.c +++ b/target/mips/tcg/translate.c @@ -24379,10 +24379,11 @@ static void decode_opc_special3_legacy(CPUMIPSState *env, DisasContext *ctx) { TCGv t0, t1; + check_dsp(ctx); + if (rt == 0) { break; } - check_dsp(ctx); t0 = tcg_temp_new(); t1 = tcg_temp_new(); From 05d9d0359e6da7dc8255712d745d079a04fa5ae5 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Date: Sat, 22 May 2021 20:16:15 +0200 Subject: [PATCH 05/15] target/mips: Do not abort on invalid instruction MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit On real hardware an invalid instruction doesn't halt the world, but usually triggers a RESERVED INSTRUCTION exception. TCG guest code shouldn't abort QEMU anyway. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20210617174323.2900831-2-f4bug@amsat.org> --- target/mips/tcg/translate.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c index 3fd0c48d77..4b7229a868 100644 --- a/target/mips/tcg/translate.c +++ b/target/mips/tcg/translate.c @@ -12151,8 +12151,8 @@ static void gen_branch(DisasContext *ctx, int insn_bytes) tcg_gen_lookup_and_goto_ptr(); break; default: - fprintf(stderr, "unknown branch 0x%x\n", proc_hflags); - abort(); + LOG_DISAS("unknown branch 0x%x\n", proc_hflags); + gen_reserved_instruction(ctx); } } } From 34b8ff25db3eff9c8c02371ac976b16389d0fcb7 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Date: Sun, 30 May 2021 09:02:16 +0200 Subject: [PATCH 06/15] target/mips: Move TCG trace events to tcg/ sub directory MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Commit a2b0a27d33e ("target/mips: Move TCG source files under tcg/ sub directory") forgot to move the trace-event file. As it only contains TCG events, move it for consistency. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20210617174323.2900831-4-f4bug@amsat.org> --- meson.build | 2 +- target/mips/{ => tcg}/trace-events | 0 target/mips/tcg/trace.h | 1 + target/mips/tcg/translate.c | 2 +- target/mips/trace.h | 1 - 5 files changed, 3 insertions(+), 3 deletions(-) rename target/mips/{ => tcg}/trace-events (100%) create mode 100644 target/mips/tcg/trace.h delete mode 100644 target/mips/trace.h diff --git a/meson.build b/meson.build index d8a92666fb..a91b39465c 100644 --- a/meson.build +++ b/meson.build @@ -1882,7 +1882,7 @@ if have_system or have_user 'target/hppa', 'target/i386', 'target/i386/kvm', - 'target/mips', + 'target/mips/tcg', 'target/ppc', 'target/riscv', 'target/s390x', diff --git a/target/mips/trace-events b/target/mips/tcg/trace-events similarity index 100% rename from target/mips/trace-events rename to target/mips/tcg/trace-events diff --git a/target/mips/tcg/trace.h b/target/mips/tcg/trace.h new file mode 100644 index 0000000000..b8c6c4568e --- /dev/null +++ b/target/mips/tcg/trace.h @@ -0,0 +1 @@ +#include "trace/trace-target_mips_tcg.h" diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c index 4b7229a868..0a4257db2a 100644 --- a/target/mips/tcg/translate.c +++ b/target/mips/tcg/translate.c @@ -31,7 +31,7 @@ #include "exec/helper-gen.h" #include "semihosting/semihost.h" -#include "target/mips/trace.h" +#include "trace.h" #include "trace-tcg.h" #include "exec/translator.h" #include "exec/log.h" diff --git a/target/mips/trace.h b/target/mips/trace.h deleted file mode 100644 index f25b88ca6f..0000000000 --- a/target/mips/trace.h +++ /dev/null @@ -1 +0,0 @@ -#include "trace/trace-target_mips.h" From a9eb3b49fb2224ca2eda514b55c5d288379460ee Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Date: Mon, 24 May 2021 09:32:16 +0200 Subject: [PATCH 07/15] target/mips: Move translate.h to tcg/ sub directory MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit We moved various TCG source files in commit a2b0a27d33e ("target/mips: Move TCG source files under tcg/ sub directory") but forgot to move the header declaring their prototypes. Do it now, since all it declares is TCG specific. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20210617174323.2900831-5-f4bug@amsat.org> --- target/mips/{ => tcg}/translate.h | 0 1 file changed, 0 insertions(+), 0 deletions(-) rename target/mips/{ => tcg}/translate.h (100%) diff --git a/target/mips/translate.h b/target/mips/tcg/translate.h similarity index 100% rename from target/mips/translate.h rename to target/mips/tcg/translate.h From 85ccd962d622475e6281ea98ab69c03de7bc37c1 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Date: Mon, 24 May 2021 14:28:08 +0200 Subject: [PATCH 08/15] target/mips: Restrict some system specific declarations to sysemu MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Commit 043715d1e0f ("target/mips: Update ITU to utilize SAARI and SAAR CP0 registers") declared itc_reconfigure() in public namespace, while it is restricted to system emulation. Similarly commit 5679479b9a1 ("target/mips: Move CP0 helpers to sysemu/cp0.c") restricted cpu_mips_soft_irq() definition to system emulation, but forgot to restrict its declaration. To avoid polluting user-mode emulation with these declarations, restrict them to sysemu. Also restrict the sysemu ITU/ITC/IRQ fields from CPUMIPSState. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20210617174323.2900831-6-f4bug@amsat.org> --- target/mips/cpu.h | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/target/mips/cpu.h b/target/mips/cpu.h index 075c24abda..1dfe69c6c0 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -1152,13 +1152,13 @@ struct CPUMIPSState { CPUMIPSMVPContext *mvp; #if !defined(CONFIG_USER_ONLY) CPUMIPSTLBContext *tlb; + void *irq[8]; + struct MIPSITUState *itu; + MemoryRegion *itc_tag; /* ITC Configuration Tags */ #endif const mips_def_t *cpu_model; - void *irq[8]; QEMUTimer *timer; /* Internal timer */ - struct MIPSITUState *itu; - MemoryRegion *itc_tag; /* ITC Configuration Tags */ target_ulong exception_base; /* ExceptionBase input to the core */ uint64_t cp0_count_ns; /* CP0_Count clock period (in nanoseconds) */ }; @@ -1316,12 +1316,16 @@ uint64_t cpu_mips_phys_to_kseg1(void *opaque, uint64_t addr); bool mips_um_ksegs_enabled(void); void mips_um_ksegs_enable(void); +#if !defined(CONFIG_USER_ONLY) + /* mips_int.c */ void cpu_mips_soft_irq(CPUMIPSState *env, int irq, int level); /* mips_itu.c */ void itc_reconfigure(struct MIPSITUState *tag); +#endif /* !CONFIG_USER_ONLY */ + /* helper.c */ target_ulong exception_resume_pc(CPUMIPSState *env); From 9f47eb54b25e67b28a85a0b3eac304f2909f10ae Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Date: Sun, 30 May 2021 00:32:16 +0200 Subject: [PATCH 09/15] target/mips: Remove SmartMIPS / MDMX unuseful comments MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit These placeholder comments for SmartMIPS and MDMX extensions have been added commit 3c824109da0 ("target-mips: microMIPS ASE support"). More than 11 years later it is safe to assume there won't be added soon, so remove these unuseful comments. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20210617174323.2900831-7-f4bug@amsat.org> --- target/mips/tcg/translate.c | 8 -------- 1 file changed, 8 deletions(-) diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c index 0a4257db2a..8b25118320 100644 --- a/target/mips/tcg/translate.c +++ b/target/mips/tcg/translate.c @@ -21578,14 +21578,6 @@ static int decode_nanomips_opc(CPUMIPSState *env, DisasContext *ctx) } -/* SmartMIPS extension to MIPS32 */ - -#if defined(TARGET_MIPS64) - -/* MDMX extension to MIPS64 */ - -#endif - /* MIPSDSP functions. */ static void gen_mipsdsp_ld(DisasContext *ctx, uint32_t opc, int rd, int base, int offset) From 916e957070e1f4b697c905d0a35984e70f106ed6 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Date: Sat, 29 May 2021 16:55:07 +0200 Subject: [PATCH 10/15] target/mips: Remove microMIPS BPOSGE32 / BPOSGE64 unuseful cases MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit These switch cases for the microMIPS BPOSGE32 / BPOSGE64 opcodes have been added commit 3c824109da0 ("target-mips: microMIPS ASE support"). More than 11 years later it is safe to assume there won't be added soon. The cases fall back to the default which generates a RESERVED INSTRUCTION, so it is safe to remove them. Functionally speaking, the patch is a no-op. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20210617174323.2900831-8-f4bug@amsat.org> --- target/mips/tcg/translate.c | 6 ------ 1 file changed, 6 deletions(-) diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c index 8b25118320..1ff0b098bc 100644 --- a/target/mips/tcg/translate.c +++ b/target/mips/tcg/translate.c @@ -14076,8 +14076,6 @@ enum { BGEZALS = 0x13, BC2F = 0x14, BC2T = 0x15, - BPOSGE64 = 0x1a, - BPOSGE32 = 0x1b, /* These overlap and are distinguished by bit16 of the instruction */ BC1F = 0x1c, BC1T = 0x1d, @@ -16121,10 +16119,6 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx) generate_exception_err(ctx, EXCP_CpU, 1); } break; - case BPOSGE64: - case BPOSGE32: - /* MIPS DSP: not implemented */ - /* Fall through */ default: MIPS_INVAL("pool32i"); gen_reserved_instruction(ctx); From e5e6f00c3154055dba99eb3b789c38dc70578111 Mon Sep 17 00:00:00 2001 From: Aleksandar Rikalo Date: Tue, 15 Jun 2021 17:22:35 +0000 Subject: [PATCH 11/15] target/mips: fix emulation of nanoMIPS BPOSGE32 instruction MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Per the "MIPS® Architecture Extension: nanoMIPS32 DSP Technical Reference Manual — Revision 0.04" p. 88 "BPOSGE32C", offset argument (imm) should be left-shifted first. This change was tested against test_dsp_r1_bposge32.c DSP test. Reported-by: Philippe Mathieu-Daudé Reviewed-by: Aleksandar Rikalo Signed-off-by: Filip Vidojevic Reviewed-by: Philippe Mathieu-Daudé Message-Id: Signed-off-by: Philippe Mathieu-Daudé --- target/mips/tcg/translate.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c index 1ff0b098bc..d248b5e5d2 100644 --- a/target/mips/tcg/translate.c +++ b/target/mips/tcg/translate.c @@ -21137,7 +21137,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx) extract32(ctx->opcode, 0, 1) << 13; gen_compute_branch_nm(ctx, OPC_BPOSGE32, 4, -1, -2, - imm); + imm << 1); } break; default: From dae7324b97ebe2c4012f299f0b6ec48ac8c1e74d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Date: Tue, 11 May 2021 12:18:06 +0200 Subject: [PATCH 12/15] target/mips: Constify host_to_mips_errno[] MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Keep host_to_mips_errno[] in .rodata by marking the array const. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20210617174323.2900831-9-f4bug@amsat.org> --- target/mips/tcg/sysemu/mips-semi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/mips/tcg/sysemu/mips-semi.c b/target/mips/tcg/sysemu/mips-semi.c index 6de60fa6dd..77108b0b1a 100644 --- a/target/mips/tcg/sysemu/mips-semi.c +++ b/target/mips/tcg/sysemu/mips-semi.c @@ -75,7 +75,7 @@ enum UHIOpenFlags { }; /* Errno values taken from asm-mips/errno.h */ -static uint16_t host_to_mips_errno[] = { +static const uint16_t host_to_mips_errno[] = { [ENAMETOOLONG] = 78, #ifdef EOVERFLOW [EOVERFLOW] = 79, From 06106772933bd215a797d28cdbff4aac5676b430 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Date: Sat, 29 May 2021 20:13:44 +0200 Subject: [PATCH 13/15] target/mips: Optimize regnames[] arrays MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Since all entries are no more than 3/4/6 bytes (including nul terminator), can save space and pie runtime relocations by declaring regnames[] as array of 3/4/6 const char. Inspired-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20210617174323.2900831-10-f4bug@amsat.org> --- target/mips/cpu.c | 2 +- target/mips/internal.h | 2 +- target/mips/tcg/msa_translate.c | 2 +- target/mips/tcg/mxu_translate.c | 4 ++-- target/mips/tcg/translate.c | 4 ++-- 5 files changed, 7 insertions(+), 7 deletions(-) diff --git a/target/mips/cpu.c b/target/mips/cpu.c index 96236abc00..d426918291 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -35,7 +35,7 @@ #include "qapi/qapi-commands-machine-target.h" #include "fpu_helper.h" -const char regnames[32][4] = { +const char regnames[32][3] = { "r0", "at", "v0", "v1", "a0", "a1", "a2", "a3", "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", diff --git a/target/mips/internal.h b/target/mips/internal.h index 18d5da64a5..eecdd10116 100644 --- a/target/mips/internal.h +++ b/target/mips/internal.h @@ -74,7 +74,7 @@ struct mips_def_t { int32_t SAARP; }; -extern const char regnames[32][4]; +extern const char regnames[32][3]; extern const char fregnames[32][4]; extern const struct mips_def_t mips_defs[]; diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translate.c index ae6587edf6..b0df4f85df 100644 --- a/target/mips/tcg/msa_translate.c +++ b/target/mips/tcg/msa_translate.c @@ -255,7 +255,7 @@ enum { OPC_BINSRI_df = (0x7 << 23) | OPC_MSA_BIT_09, }; -static const char * const msaregnames[] = { +static const char msaregnames[][6] = { "w0.d0", "w0.d1", "w1.d0", "w1.d1", "w2.d0", "w2.d1", "w3.d0", "w3.d1", "w4.d0", "w4.d1", "w5.d0", "w5.d1", diff --git a/target/mips/tcg/mxu_translate.c b/target/mips/tcg/mxu_translate.c index fb0a811af6..963d4ba8b1 100644 --- a/target/mips/tcg/mxu_translate.c +++ b/target/mips/tcg/mxu_translate.c @@ -447,9 +447,9 @@ enum { static TCGv mxu_gpr[NUMBER_OF_MXU_REGISTERS - 1]; static TCGv mxu_CR; -static const char * const mxuregnames[] = { +static const char mxuregnames[][4] = { "XR1", "XR2", "XR3", "XR4", "XR5", "XR6", "XR7", "XR8", - "XR9", "XR10", "XR11", "XR12", "XR13", "XR14", "XR15", "MXU_CR", + "XR9", "XR10", "XR11", "XR12", "XR13", "XR14", "XR15", "XCR", }; void mxu_translate_init(void) diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c index d248b5e5d2..b4a454ec09 100644 --- a/target/mips/tcg/translate.c +++ b/target/mips/tcg/translate.c @@ -1280,11 +1280,11 @@ TCGv_i64 fpu_f64[32]; #define DISAS_STOP DISAS_TARGET_0 #define DISAS_EXIT DISAS_TARGET_1 -static const char * const regnames_HI[] = { +static const char regnames_HI[][4] = { "HI0", "HI1", "HI2", "HI3", }; -static const char * const regnames_LO[] = { +static const char regnames_LO[][4] = { "LO0", "LO1", "LO2", "LO3", }; From 525ea877b27d933eaac69b32c75b8861779811cf Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Date: Sat, 29 May 2021 20:12:16 +0200 Subject: [PATCH 14/15] target/mips: Remove pointless gen_msa() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Only trans_MSA() calls gen_msa(), inline it to simplify. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20210617174636.2902654-2-f4bug@amsat.org> --- target/mips/tcg/msa_translate.c | 7 +------ 1 file changed, 1 insertion(+), 6 deletions(-) diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translate.c index b0df4f85df..9df4497c88 100644 --- a/target/mips/tcg/msa_translate.c +++ b/target/mips/tcg/msa_translate.c @@ -2162,7 +2162,7 @@ static void gen_msa_vec(DisasContext *ctx) } } -static void gen_msa(DisasContext *ctx) +static bool trans_MSA(DisasContext *ctx, arg_MSA *a) { uint32_t opcode = ctx->opcode; @@ -2258,11 +2258,6 @@ static void gen_msa(DisasContext *ctx) gen_reserved_instruction(ctx); break; } -} - -static bool trans_MSA(DisasContext *ctx, arg_MSA *a) -{ - gen_msa(ctx); return true; } From f5c6ee0c6b7b4b79b52a1614a808633dbb694de4 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Date: Sat, 29 May 2021 20:06:13 +0200 Subject: [PATCH 15/15] target/mips: Merge msa32/msa64 decodetree definitions MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit We don't need to maintain 2 sets of decodetree definitions. Merge them into a single file. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20210617174636.2902654-3-f4bug@amsat.org> --- target/mips/tcg/meson.build | 3 +-- target/mips/tcg/{msa32.decode => msa.decode} | 8 +++++--- target/mips/tcg/msa64.decode | 17 ----------------- target/mips/tcg/msa_translate.c | 14 ++++---------- 4 files changed, 10 insertions(+), 32 deletions(-) rename target/mips/tcg/{msa32.decode => msa.decode} (74%) delete mode 100644 target/mips/tcg/msa64.decode diff --git a/target/mips/tcg/meson.build b/target/mips/tcg/meson.build index 5d8acbaf0d..bf4001e574 100644 --- a/target/mips/tcg/meson.build +++ b/target/mips/tcg/meson.build @@ -1,8 +1,7 @@ gen = [ decodetree.process('mips32r6.decode', extra_args: '--static-decode=decode_mips32r6'), decodetree.process('mips64r6.decode', extra_args: '--static-decode=decode_mips64r6'), - decodetree.process('msa32.decode', extra_args: '--static-decode=decode_msa32'), - decodetree.process('msa64.decode', extra_args: '--static-decode=decode_msa64'), + decodetree.process('msa.decode', extra_args: '--decode=decode_ase_msa'), decodetree.process('tx79.decode', extra_args: '--static-decode=decode_tx79'), ] diff --git a/target/mips/tcg/msa32.decode b/target/mips/tcg/msa.decode similarity index 74% rename from target/mips/tcg/msa32.decode rename to target/mips/tcg/msa.decode index ca200e373b..bf132e36b9 100644 --- a/target/mips/tcg/msa32.decode +++ b/target/mips/tcg/msa.decode @@ -6,9 +6,10 @@ # # Reference: # MIPS Architecture for Programmers Volume IV-j -# The MIPS32 SIMD Architecture Module, Revision 1.12 -# (Document Number: MD00866-2B-MSA32-AFP-01.12) -# +# - The MIPS32 SIMD Architecture Module, Revision 1.12 +# (Document Number: MD00866-2B-MSA32-AFP-01.12) +# - The MIPS64 SIMD Architecture Module, Revision 1.12 +# (Document Number: MD00868-1D-MSA64-AFP-01.12) &rtype rs rt rd sa @@ -19,6 +20,7 @@ @bz_df ...... ... df:2 wt:5 s16:16 &msa_bz LSA 000000 ..... ..... ..... 000 .. 000101 @lsa +DLSA 000000 ..... ..... ..... 000 .. 010101 @lsa BZ_V 010001 01011 ..... ................ @bz BNZ_V 010001 01111 ..... ................ @bz diff --git a/target/mips/tcg/msa64.decode b/target/mips/tcg/msa64.decode deleted file mode 100644 index d2442474d0..0000000000 --- a/target/mips/tcg/msa64.decode +++ /dev/null @@ -1,17 +0,0 @@ -# MIPS SIMD Architecture Module instruction set -# -# Copyright (C) 2020 Philippe Mathieu-Daudé -# -# SPDX-License-Identifier: LGPL-2.1-or-later -# -# Reference: -# MIPS Architecture for Programmers Volume IV-j -# The MIPS64 SIMD Architecture Module, Revision 1.12 -# (Document Number: MD00868-1D-MSA64-AFP-01.12) -# - -&rtype rs rt rd sa !extern - -@lsa ...... rs:5 rt:5 rd:5 ... sa:2 ...... &rtype - -DLSA 000000 ..... ..... ..... 000 .. 010101 @lsa diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translate.c index 9df4497c88..eed2eca6c9 100644 --- a/target/mips/tcg/msa_translate.c +++ b/target/mips/tcg/msa_translate.c @@ -18,8 +18,7 @@ #include "internal.h" /* Include the auto-generated decoder. */ -#include "decode-msa32.c.inc" -#include "decode-msa64.c.inc" +#include "decode-msa.c.inc" #define OPC_MSA (0x1E << 26) @@ -2269,13 +2268,8 @@ static bool trans_LSA(DisasContext *ctx, arg_rtype *a) static bool trans_DLSA(DisasContext *ctx, arg_rtype *a) { + if (TARGET_LONG_BITS != 64) { + return false; + } return gen_dlsa(ctx, a->rd, a->rt, a->rs, a->sa); } - -bool decode_ase_msa(DisasContext *ctx, uint32_t insn) -{ - if (TARGET_LONG_BITS == 64 && decode_msa64(ctx, insn)) { - return true; - } - return decode_msa32(ctx, insn); -}