8250: throttle TX-completion IRQs
(Jan Kiszka) git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4335 c046a42c-6fe2-441c-8c8c-71466251a162
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55
hw/serial.c
55
hw/serial.c
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@ -25,6 +25,7 @@
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#include "qemu-char.h"
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#include "isa.h"
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#include "pc.h"
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#include "qemu-timer.h"
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//#define DEBUG_SERIAL
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@ -73,6 +74,13 @@
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#define UART_LSR_OE 0x02 /* Overrun error indicator */
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#define UART_LSR_DR 0x01 /* Receiver data ready */
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/*
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* Delay TX IRQ after sending as much characters as the given interval would
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* contain on real hardware. This avoids overloading the guest if it processes
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* its output buffer in a loop inside the TX IRQ handler.
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*/
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#define THROTTLE_TX_INTERVAL 10 /* ms */
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struct SerialState {
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uint16_t divider;
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uint8_t rbr; /* receive register */
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@ -91,6 +99,8 @@ struct SerialState {
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int last_break_enable;
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target_phys_addr_t base;
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int it_shift;
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QEMUTimer *tx_timer;
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int tx_burst;
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};
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static void serial_receive_byte(SerialState *s, int ch);
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@ -111,6 +121,28 @@ static void serial_update_irq(SerialState *s)
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}
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}
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static void serial_tx_done(void *opaque)
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{
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SerialState *s = opaque;
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if (s->tx_burst < 0) {
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uint16_t divider;
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if (s->divider)
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divider = s->divider;
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else
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divider = 1;
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/* We assume 10 bits/char, OK for this purpose. */
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s->tx_burst = THROTTLE_TX_INTERVAL * 1000 /
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(1000000 * 10 / (115200 / divider));
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}
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s->thr_ipending = 1;
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s->lsr |= UART_LSR_THRE;
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s->lsr |= UART_LSR_TEMT;
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serial_update_irq(s);
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}
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static void serial_update_parameters(SerialState *s)
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{
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int speed, parity, data_bits, stop_bits;
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@ -166,15 +198,18 @@ static void serial_ioport_write(void *opaque, uint32_t addr, uint32_t val)
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if (!(s->mcr & UART_MCR_LOOP)) {
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/* when not in loopback mode, send the char */
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qemu_chr_write(s->chr, &ch, 1);
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}
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s->thr_ipending = 1;
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s->lsr |= UART_LSR_THRE;
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s->lsr |= UART_LSR_TEMT;
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serial_update_irq(s);
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if (s->mcr & UART_MCR_LOOP) {
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} else {
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/* in loopback mode, say that we just received a char */
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serial_receive_byte(s, ch);
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}
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if (s->tx_burst > 0) {
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s->tx_burst--;
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serial_tx_done(s);
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} else if (s->tx_burst == 0) {
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s->tx_burst--;
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qemu_mod_timer(s->tx_timer, qemu_get_clock(vm_clock) +
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ticks_per_sec * THROTTLE_TX_INTERVAL / 1000);
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}
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}
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break;
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case 1:
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@ -387,6 +422,10 @@ SerialState *serial_init(int base, qemu_irq irq, CharDriverState *chr)
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return NULL;
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s->irq = irq;
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s->tx_timer = qemu_new_timer(vm_clock, serial_tx_done, s);
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if (!s->tx_timer)
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return NULL;
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qemu_register_reset(serial_reset, s);
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serial_reset(s);
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@ -486,6 +525,10 @@ SerialState *serial_mm_init (target_phys_addr_t base, int it_shift,
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s->base = base;
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s->it_shift = it_shift;
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s->tx_timer = qemu_new_timer(vm_clock, serial_tx_done, s);
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if (!s->tx_timer)
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return NULL;
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qemu_register_reset(serial_reset, s);
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serial_reset(s);
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