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qemu-patch-raspberry4
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tcg: Implement multiword multiply helpers 

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
stable-1.5
Richard Henderson 2013-02-19 23:51:55 -08:00 committed by Blue Swirl
parent 3c51a98507
commit 696a8be6a0
3 changed files with 101 additions and 1 deletions
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16
tcg-runtime.c
View File

@ -22,7 +22,7 @@
* THE SOFTWARE.
*/
#include <stdint.h>
#include "qemu/host-utils.h"
#include "tcg/tcg-runtime.h"
/* 32-bit helpers */
@ -83,3 +83,17 @@ uint64_t tcg_helper_remu_i64(uint64_t arg1, uint64_t arg2)
{
return arg1 % arg2;
}
uint64_t tcg_helper_muluh_i64(uint64_t arg1, uint64_t arg2)
{
uint64_t l, h;
mulu64(&l, &h, arg1, arg2);
return h;
}
int64_t tcg_helper_mulsh_i64(int64_t arg1, int64_t arg2)
{
uint64_t l, h;
muls64(&l, &h, arg1, arg2);
return h;
}

84
tcg/tcg-op.h
View File

@ -2332,6 +2332,86 @@ static inline void tcg_gen_movcond_i64(TCGCond cond, TCGv_i64 ret,
#endif
}
static inline void tcg_gen_mulu2_i32(TCGv_i32 rl, TCGv_i32 rh,
TCGv_i32 arg1, TCGv_i32 arg2)
{
if (TCG_TARGET_HAS_mulu2_i32) {
tcg_gen_op4_i32(INDEX_op_mulu2_i32, rl, rh, arg1, arg2);
/* Allow the optimizer room to replace mulu2 with two moves. */
tcg_gen_op0(INDEX_op_nop);
} else {
TCGv_i64 t0 = tcg_temp_new_i64();
TCGv_i64 t1 = tcg_temp_new_i64();
tcg_gen_extu_i32_i64(t0, arg1);
tcg_gen_extu_i32_i64(t1, arg2);
tcg_gen_mul_i64(t0, t0, t1);
tcg_gen_extr_i64_i32(rl, rh, t0);
tcg_temp_free_i64(t0);
tcg_temp_free_i64(t1);
}
}
static inline void tcg_gen_muls2_i32(TCGv_i32 rl, TCGv_i32 rh,
TCGv_i32 arg1, TCGv_i32 arg2)
{
if (TCG_TARGET_HAS_muls2_i32) {
tcg_gen_op4_i32(INDEX_op_muls2_i32, rl, rh, arg1, arg2);
/* Allow the optimizer room to replace muls2 with two moves. */
tcg_gen_op0(INDEX_op_nop);
} else {
TCGv_i64 t0 = tcg_temp_new_i64();
TCGv_i64 t1 = tcg_temp_new_i64();
tcg_gen_ext_i32_i64(t0, arg1);
tcg_gen_ext_i32_i64(t1, arg2);
tcg_gen_mul_i64(t0, t0, t1);
tcg_gen_extr_i64_i32(rl, rh, t0);
tcg_temp_free_i64(t0);
tcg_temp_free_i64(t1);
}
}
static inline void tcg_gen_mulu2_i64(TCGv_i64 rl, TCGv_i64 rh,
TCGv_i64 arg1, TCGv_i64 arg2)
{
if (TCG_TARGET_HAS_mulu2_i64) {
tcg_gen_op4_i64(INDEX_op_mulu2_i64, rl, rh, arg1, arg2);
/* Allow the optimizer room to replace mulu2 with two moves. */
tcg_gen_op0(INDEX_op_nop);
} else {
TCGv_i64 t0 = tcg_temp_new_i64();
int sizemask = 0;
/* Return value and both arguments are 64-bit and unsigned. */
sizemask |= tcg_gen_sizemask(0, 1, 0);
sizemask |= tcg_gen_sizemask(1, 1, 0);
sizemask |= tcg_gen_sizemask(2, 1, 0);
tcg_gen_mul_i64(t0, arg1, arg2);
tcg_gen_helper64(tcg_helper_muluh_i64, sizemask, rh, arg1, arg2);
tcg_gen_mov_i64(rl, t0);
tcg_temp_free_i64(t0);
}
}
static inline void tcg_gen_muls2_i64(TCGv_i64 rl, TCGv_i64 rh,
TCGv_i64 arg1, TCGv_i64 arg2)
{
if (TCG_TARGET_HAS_muls2_i64) {
tcg_gen_op4_i64(INDEX_op_muls2_i64, rl, rh, arg1, arg2);
/* Allow the optimizer room to replace muls2 with two moves. */
tcg_gen_op0(INDEX_op_nop);
} else {
TCGv_i64 t0 = tcg_temp_new_i64();
int sizemask = 0;
/* Return value and both arguments are 64-bit and signed. */
sizemask |= tcg_gen_sizemask(0, 1, 1);
sizemask |= tcg_gen_sizemask(1, 1, 1);
sizemask |= tcg_gen_sizemask(2, 1, 1);
tcg_gen_mul_i64(t0, arg1, arg2);
tcg_gen_helper64(tcg_helper_mulsh_i64, sizemask, rh, arg1, arg2);
tcg_gen_mov_i64(rl, t0);
tcg_temp_free_i64(t0);
}
}
/***************************************/
/* QEMU specific operations. Their type depend on the QEMU CPU
type. */
@ -2659,6 +2739,8 @@ static inline void tcg_gen_qemu_st64(TCGv_i64 arg, TCGv addr, int mem_index)
#define tcg_const_tl tcg_const_i64
#define tcg_const_local_tl tcg_const_local_i64
#define tcg_gen_movcond_tl tcg_gen_movcond_i64
#define tcg_gen_mulu2_tl tcg_gen_mulu2_i64
#define tcg_gen_muls2_tl tcg_gen_muls2_i64
#else
#define tcg_gen_movi_tl tcg_gen_movi_i32
#define tcg_gen_mov_tl tcg_gen_mov_i32
@ -2732,6 +2814,8 @@ static inline void tcg_gen_qemu_st64(TCGv_i64 arg, TCGv addr, int mem_index)
#define tcg_const_tl tcg_const_i32
#define tcg_const_local_tl tcg_const_local_i32
#define tcg_gen_movcond_tl tcg_gen_movcond_i32
#define tcg_gen_mulu2_tl tcg_gen_mulu2_i32
#define tcg_gen_muls2_tl tcg_gen_muls2_i32
#endif
#if TCG_TARGET_REG_BITS == 32

2
tcg/tcg-runtime.h
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@ -12,7 +12,9 @@ int64_t tcg_helper_shr_i64(int64_t arg1, int64_t arg2);
int64_t tcg_helper_sar_i64(int64_t arg1, int64_t arg2);
int64_t tcg_helper_div_i64(int64_t arg1, int64_t arg2);
int64_t tcg_helper_rem_i64(int64_t arg1, int64_t arg2);
int64_t tcg_helper_mulsh_i64(int64_t arg1, int64_t arg2);
uint64_t tcg_helper_divu_i64(uint64_t arg1, uint64_t arg2);
uint64_t tcg_helper_remu_i64(uint64_t arg1, uint64_t arg2);
uint64_t tcg_helper_muluh_i64(uint64_t arg1, uint64_t arg2);
#endif