RISC-V Patches for the 3.1 Soft Freeze, Part 2
This tag contains a few simple patches that I'd like to target for the QEMU soft freeze. There's only one code change: a fix to our PMP implementation that avoids an internal truncation while computing a partial PMP read. I also have two updates to the MAINTAINERS file: one to add Alistair as a RISC-V maintainer, and one to add our newly created mailing list. -----BEGIN PGP SIGNATURE----- iQJHBAABCAAxFiEEAM520YNJYN/OiG3470yhUCzLq0EFAlvYoC0THHBhbG1lckBk YWJiZWx0LmNvbQAKCRDvTKFQLMurQbo0D/9o24meWSB+5tmN47A9Uztu1pyHoMoA oWzYaYXU7tUyLgeCkavyceWpjvpn+NDbVNzWWOxCsArAOezxJabUgj++xhqgouJ8 lJwLehTJG1NNXH7rUAOPI9IV16m3oQT6oNmvu2XxT5VaMXJYuHzXqPaAu8J5iYkl SJBWvBJoGP42iYsjezm5j/C/WspK6W/OH73IbIxkD+NDoiFNqhTA+4ar00Xd4uo2 E3Fm/y0Lzk61lKq6MfRn8kSdsbbGDJbIfpwG4DRBSqk0naSQc9dvG5toEavgyiOk FmdCBcD+yza6VEIlpe2gcF4lEHILHbM4BUUE0Ykw8muDRFM2ebjIcpSf8GzsLVeZ uzmKVRiDfzGzJBhXtN4uAfqHH/3fak+ROHcUU1LSAoGS8z2vl5v4RK++Ew1CsRfs /jFh1+3+rVHTNiCkMewImRPihprFQS7S0Wj+i7FYexYU6TwZ9tQ8NIdboJQOpsPf DRGxujt32t2FCiqHEMuQ28V6MBVN7xXU92RocX0u+C+2YaLKsOC2PkBa75qTAV/8 T95ofKL2DtIMOPQytB0b38RZC881DMCKC/qS4DIYKCFUV3vo92HFt2cmvVuHAuGQ wM4mmLCLUdjjnV/6SrMkG+sBV2RMitwACvkeGBgHmD+IVpAGIjXyAk7k4T0ZMLmh nX/LAwdK7cFO7g== =PuPt -----END PGP SIGNATURE----- Merge remote-tracking branch 'remotes/riscv/tags/riscv-for-master-3.1-sf1' into staging RISC-V Patches for the 3.1 Soft Freeze, Part 2 This tag contains a few simple patches that I'd like to target for the QEMU soft freeze. There's only one code change: a fix to our PMP implementation that avoids an internal truncation while computing a partial PMP read. I also have two updates to the MAINTAINERS file: one to add Alistair as a RISC-V maintainer, and one to add our newly created mailing list. # gpg: Signature made Tue 30 Oct 2018 18:17:17 GMT # gpg: using RSA key EF4CA1502CCBAB41 # gpg: Good signature from "Palmer Dabbelt <palmer@dabbelt.com>" # gpg: aka "Palmer Dabbelt <palmer@sifive.com>" # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 00CE 76D1 8349 60DF CE88 6DF8 EF4C A150 2CCB AB41 * remotes/riscv/tags/riscv-for-master-3.1-sf1: Add qemu-riscv@nongnu.org as the RISC-V list Add Alistair as a RISC-V Maintainer target/riscv/pmp.c: pmpcfg_csr_read returns bogus value on RV64 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
commit
69e2d03843
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@ -241,8 +241,10 @@ F: disas/ppc.c
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RISC-V
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RISC-V
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M: Michael Clark <mjc@sifive.com>
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M: Michael Clark <mjc@sifive.com>
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M: Palmer Dabbelt <palmer@sifive.com>
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M: Palmer Dabbelt <palmer@sifive.com>
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M: Alistair Francis <Alistair.Francis@wdc.com>
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M: Sagar Karandikar <sagark@eecs.berkeley.edu>
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M: Sagar Karandikar <sagark@eecs.berkeley.edu>
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M: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
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M: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
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L: qemu-riscv@nongnu.org
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S: Maintained
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S: Maintained
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F: target/riscv/
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F: target/riscv/
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F: hw/riscv/
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F: hw/riscv/
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@ -325,7 +325,7 @@ target_ulong pmpcfg_csr_read(CPURISCVState *env, uint32_t reg_index)
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{
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{
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int i;
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int i;
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target_ulong cfg_val = 0;
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target_ulong cfg_val = 0;
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uint8_t val = 0;
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target_ulong val = 0;
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for (i = 0; i < sizeof(target_ulong); i++) {
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for (i = 0; i < sizeof(target_ulong); i++) {
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val = pmp_read_cfg(env, (reg_index * sizeof(target_ulong)) + i);
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val = pmp_read_cfg(env, (reg_index * sizeof(target_ulong)) + i);
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