target-m68k: define ext_opsize
Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <rth@twiddle.net> Message-Id: <20170611231633.32582-4-laurent@vivier.eu>
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@ -669,6 +669,21 @@ static inline int insn_opsize(int insn)
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}
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}
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static inline int ext_opsize(int ext, int pos)
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{
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switch ((ext >> pos) & 7) {
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case 0: return OS_LONG;
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case 1: return OS_SINGLE;
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case 2: return OS_EXTENDED;
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case 3: return OS_PACKED;
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case 4: return OS_WORD;
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case 5: return OS_DOUBLE;
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case 6: return OS_BYTE;
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default:
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g_assert_not_reached();
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}
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}
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/* Assign value to a register. If the width is less than the register width
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only the low part of the register is set. */
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static void gen_partset_reg(int opsize, TCGv reg, TCGv val)
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@ -4111,20 +4126,19 @@ DISAS_INSN(fpu)
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tmp32 = tcg_temp_new_i32();
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/* fmove */
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/* ??? TODO: Proper behavior on overflow. */
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switch ((ext >> 10) & 7) {
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case 0:
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opsize = OS_LONG;
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opsize = ext_opsize(ext, 10);
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switch (opsize) {
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case OS_LONG:
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gen_helper_f64_to_i32(tmp32, cpu_env, src);
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break;
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case 1:
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opsize = OS_SINGLE;
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case OS_SINGLE:
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gen_helper_f64_to_f32(tmp32, cpu_env, src);
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break;
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case 4:
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opsize = OS_WORD;
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case OS_WORD:
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gen_helper_f64_to_i32(tmp32, cpu_env, src);
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break;
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case 5: /* OS_DOUBLE */
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case OS_DOUBLE:
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tcg_gen_mov_i32(tmp32, AREG(insn, 0));
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switch ((insn >> 3) & 7) {
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case 2:
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@ -4153,8 +4167,7 @@ DISAS_INSN(fpu)
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}
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tcg_temp_free_i32(tmp32);
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return;
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case 6:
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opsize = OS_BYTE;
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case OS_BYTE:
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gen_helper_f64_to_i32(tmp32, cpu_env, src);
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break;
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default:
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@ -4227,15 +4240,7 @@ DISAS_INSN(fpu)
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}
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if (ext & (1 << 14)) {
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/* Source effective address. */
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switch ((ext >> 10) & 7) {
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case 0: opsize = OS_LONG; break;
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case 1: opsize = OS_SINGLE; break;
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case 4: opsize = OS_WORD; break;
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case 5: opsize = OS_DOUBLE; break;
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case 6: opsize = OS_BYTE; break;
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default:
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goto undef;
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}
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opsize = ext_opsize(ext, 10);
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if (opsize == OS_DOUBLE) {
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tmp32 = tcg_temp_new_i32();
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tcg_gen_mov_i32(tmp32, AREG(insn, 0));
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