hw/intc/arm_gic: Add external IRQ lines for VIRQ and VFIQ
Augment the GIC's QOM device interface by adding two new sets of sysbus IRQ lines, to signal VIRQ and VFIQ to each CPU. We never use these, but it's helpful to keep the v2-and-earlier GIC's external interface in line with that of the GICv3 to avoid board code having to add extra code conditional on which version of the GIC is in use. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1483977924-14522-3-git-send-email-peter.maydell@linaro.org
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@ -110,6 +110,12 @@ void gic_init_irqs_and_mmio(GICState *s, qemu_irq_handler handler,
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for (i = 0; i < s->num_cpu; i++) {
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sysbus_init_irq(sbd, &s->parent_fiq[i]);
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}
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for (i = 0; i < s->num_cpu; i++) {
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sysbus_init_irq(sbd, &s->parent_virq[i]);
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}
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for (i = 0; i < s->num_cpu; i++) {
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sysbus_init_irq(sbd, &s->parent_vfiq[i]);
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}
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/* Distributor */
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memory_region_init_io(&s->iomem, OBJECT(s), ops, s, "gic_dist", 0x1000);
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@ -55,6 +55,8 @@ typedef struct GICState {
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qemu_irq parent_irq[GIC_NCPU];
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qemu_irq parent_fiq[GIC_NCPU];
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qemu_irq parent_virq[GIC_NCPU];
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qemu_irq parent_vfiq[GIC_NCPU];
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/* GICD_CTLR; for a GIC with the security extensions the NS banked version
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* of this register is just an alias of bit 1 of the S banked version.
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*/
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