ARM timers qdev conversion

Signed-off-by: Paul Brook <paul@codesourcery.com>

hw/arm_timer.c

@@ -7,9 +7,8 @@
  * This code is licenced under the GPL.
  */
 
-#include "hw.h"
+#include "sysbus.h"
 #include "qemu-timer.h"
-#include "primecell.h"
 
 /* Common timer implementation.  */
 
@@ -164,13 +163,12 @@ static int arm_timer_load(QEMUFile *f, void *opaque, int version_id)
     return 0;
 }
 
-static void *arm_timer_init(uint32_t freq, qemu_irq irq)
+static arm_timer_state *arm_timer_init(uint32_t freq)
 {
     arm_timer_state *s;
     QEMUBH *bh;
 
     s = (arm_timer_state *)qemu_mallocz(sizeof(arm_timer_state));
-    s->irq = irq;
     s->freq = freq;
     s->control = TIMER_CTRL_IE;
 
@@ -186,7 +184,8 @@ static void *arm_timer_init(uint32_t freq, qemu_irq irq)
    Integrator/CP timer modules.  */
 
 typedef struct {
-    void *timer[2];
+    SysBusDevice busdev;
+    arm_timer_state *timer[2];
     int level[2];
     qemu_irq irq;
 } sp804_state;
@@ -255,22 +254,23 @@ static int sp804_load(QEMUFile *f, void *opaque, int version_id)
     return 0;
 }
 
-void sp804_init(uint32_t base, qemu_irq irq)
+static void sp804_init(SysBusDevice *dev)
 {
     int iomemtype;
-    sp804_state *s;
+    sp804_state *s = FROM_SYSBUS(sp804_state, dev);
     qemu_irq *qi;
 
-    s = (sp804_state *)qemu_mallocz(sizeof(sp804_state));
     qi = qemu_allocate_irqs(sp804_set_irq, s, 2);
-    s->irq = irq;
+    sysbus_init_irq(dev, &s->irq);
     /* ??? The timers are actually configurable between 32kHz and 1MHz, but
        we don't implement that.  */
-    s->timer[0] = arm_timer_init(1000000, qi[0]);
-    s->timer[1] = arm_timer_init(1000000, qi[1]);
+    s->timer[0] = arm_timer_init(1000000);
+    s->timer[1] = arm_timer_init(1000000);
+    s->timer[0]->irq = qi[0];
+    s->timer[1]->irq = qi[1];
     iomemtype = cpu_register_io_memory(0, sp804_readfn,
                                        sp804_writefn, s);
-    cpu_register_physical_memory(base, 0x00001000, iomemtype);
+    sysbus_init_mmio(dev, 0x1000, iomemtype);
     register_savevm("sp804", -1, 1, sp804_save, sp804_load, s);
 }
 
@@ -278,7 +278,8 @@ void sp804_init(uint32_t base, qemu_irq irq)
 /* Integrator/CP timer module.  */
 
 typedef struct {
-    void *timer[3];
+    SysBusDevice busdev;
+    arm_timer_state *timer[3];
 } icp_pit_state;
 
 static uint32_t icp_pit_read(void *opaque, target_phys_addr_t offset)
@@ -322,21 +323,32 @@ static CPUWriteMemoryFunc *icp_pit_writefn[] = {
    icp_pit_write
 };
 
-void icp_pit_init(uint32_t base, qemu_irq *pic, int irq)
+static void icp_pit_init(SysBusDevice *dev)
 {
     int iomemtype;
-    icp_pit_state *s;
+    icp_pit_state *s = FROM_SYSBUS(icp_pit_state, dev);
 
-    s = (icp_pit_state *)qemu_mallocz(sizeof(icp_pit_state));
     /* Timer 0 runs at the system clock speed (40MHz).  */
-    s->timer[0] = arm_timer_init(40000000, pic[irq]);
+    s->timer[0] = arm_timer_init(40000000);
     /* The other two timers run at 1MHz.  */
-    s->timer[1] = arm_timer_init(1000000, pic[irq + 1]);
-    s->timer[2] = arm_timer_init(1000000, pic[irq + 2]);
+    s->timer[1] = arm_timer_init(1000000);
+    s->timer[2] = arm_timer_init(1000000);
+
+    sysbus_init_irq(dev, &s->timer[0]->irq);
+    sysbus_init_irq(dev, &s->timer[1]->irq);
+    sysbus_init_irq(dev, &s->timer[2]->irq);
 
     iomemtype = cpu_register_io_memory(0, icp_pit_readfn,
                                        icp_pit_writefn, s);
-    cpu_register_physical_memory(base, 0x00001000, iomemtype);
+    sysbus_init_mmio(dev, 0x1000, iomemtype);
     /* This device has no state to save/restore.  The component timers will
        save themselves.  */
 }
+
+static void arm_timer_register_devices(void)
+{
+    sysbus_register_dev("integrator_pit", sizeof(icp_pit_state), icp_pit_init);
+    sysbus_register_dev("sp804", sizeof(sp804_state), sp804_init);
+}
+
+device_init(arm_timer_register_devices)

hw/integratorcp.c

@@ -486,8 +486,9 @@ static void integratorcp_init(ram_addr_t ram_size,
     for (i = 0; i < 32; i++) {
         pic[i] = qdev_get_irq_sink(dev, i);
     }
-    dev = sysbus_create_simple("integrator_pic", 0xca000000, pic[26]);
-    icp_pit_init(0x13000000, pic, 5);
+    sysbus_create_simple("integrator_pic", 0xca000000, pic[26]);
+    sysbus_create_varargs("integrator_pit", 0x13000000,
+                          pic[5], pic[6], pic[7], NULL);
     sysbus_create_simple("pl031", 0x15000000, pic[8]);
     sysbus_create_simple("pl011", 0x16000000, pic[1]);
     sysbus_create_simple("pl011", 0x17000000, pic[2]);

hw/primecell.h

@@ -26,10 +26,6 @@ qemu_irq *realview_gic_init(uint32_t base, qemu_irq parent_irq);
 /* mpcore.c */
 extern qemu_irq *mpcore_irq_init(qemu_irq *cpu_irq);
 
-/* arm-timer.c */
-void sp804_init(uint32_t base, qemu_irq irq);
-void icp_pit_init(uint32_t base, qemu_irq *pic, int irq);
-
 /* arm_sysctl.c */
 void arm_sysctl_init(uint32_t base, uint32_t sys_id);
 

hw/realview.c

@@ -91,8 +91,8 @@ static void realview_init(ram_addr_t ram_size,
     /* DMA controller is optional, apparently.  */
     pl080_init(0x10030000, pic[24], 2);
 
-    sp804_init(0x10011000, pic[4]);
-    sp804_init(0x10012000, pic[5]);
+    sysbus_create_simple("sp804", 0x10011000, pic[4]);
+    sysbus_create_simple("sp804", 0x10012000, pic[5]);
 
     sysbus_create_simple("pl110_versatile", 0x10020000, pic[23]);
 

hw/versatilepb.c

@@ -216,8 +216,8 @@ static void versatile_init(ram_addr_t ram_size,
     sysbus_create_simple("pl011", 0x10009000, sic[6]);
 
     pl080_init(0x10130000, pic[17], 8);
-    sp804_init(0x101e2000, pic[4]);
-    sp804_init(0x101e3000, pic[5]);
+    sysbus_create_simple("sp804", 0x101e2000, pic[4]);
+    sysbus_create_simple("sp804", 0x101e3000, pic[5]);
 
     /* The versatile/PB actually has a modified Color LCD controller
        that includes hardware cursor support from the PL111.  */