ARM timers qdev conversion
Signed-off-by: Paul Brook <paul@codesourcery.com>
This commit is contained in:
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a7086888fc
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6a824ec3d2
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@ -7,9 +7,8 @@
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* This code is licenced under the GPL.
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* This code is licenced under the GPL.
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*/
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*/
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#include "hw.h"
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#include "sysbus.h"
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#include "qemu-timer.h"
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#include "qemu-timer.h"
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#include "primecell.h"
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/* Common timer implementation. */
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/* Common timer implementation. */
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@ -164,13 +163,12 @@ static int arm_timer_load(QEMUFile *f, void *opaque, int version_id)
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return 0;
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return 0;
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}
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}
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static void *arm_timer_init(uint32_t freq, qemu_irq irq)
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static arm_timer_state *arm_timer_init(uint32_t freq)
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{
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{
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arm_timer_state *s;
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arm_timer_state *s;
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QEMUBH *bh;
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QEMUBH *bh;
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s = (arm_timer_state *)qemu_mallocz(sizeof(arm_timer_state));
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s = (arm_timer_state *)qemu_mallocz(sizeof(arm_timer_state));
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s->irq = irq;
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s->freq = freq;
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s->freq = freq;
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s->control = TIMER_CTRL_IE;
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s->control = TIMER_CTRL_IE;
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@ -186,7 +184,8 @@ static void *arm_timer_init(uint32_t freq, qemu_irq irq)
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Integrator/CP timer modules. */
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Integrator/CP timer modules. */
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typedef struct {
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typedef struct {
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void *timer[2];
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SysBusDevice busdev;
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arm_timer_state *timer[2];
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int level[2];
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int level[2];
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qemu_irq irq;
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qemu_irq irq;
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} sp804_state;
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} sp804_state;
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@ -255,22 +254,23 @@ static int sp804_load(QEMUFile *f, void *opaque, int version_id)
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return 0;
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return 0;
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}
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}
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void sp804_init(uint32_t base, qemu_irq irq)
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static void sp804_init(SysBusDevice *dev)
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{
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{
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int iomemtype;
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int iomemtype;
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sp804_state *s;
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sp804_state *s = FROM_SYSBUS(sp804_state, dev);
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qemu_irq *qi;
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qemu_irq *qi;
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s = (sp804_state *)qemu_mallocz(sizeof(sp804_state));
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qi = qemu_allocate_irqs(sp804_set_irq, s, 2);
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qi = qemu_allocate_irqs(sp804_set_irq, s, 2);
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s->irq = irq;
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sysbus_init_irq(dev, &s->irq);
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/* ??? The timers are actually configurable between 32kHz and 1MHz, but
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/* ??? The timers are actually configurable between 32kHz and 1MHz, but
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we don't implement that. */
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we don't implement that. */
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s->timer[0] = arm_timer_init(1000000, qi[0]);
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s->timer[0] = arm_timer_init(1000000);
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s->timer[1] = arm_timer_init(1000000, qi[1]);
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s->timer[1] = arm_timer_init(1000000);
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s->timer[0]->irq = qi[0];
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s->timer[1]->irq = qi[1];
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iomemtype = cpu_register_io_memory(0, sp804_readfn,
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iomemtype = cpu_register_io_memory(0, sp804_readfn,
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sp804_writefn, s);
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sp804_writefn, s);
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cpu_register_physical_memory(base, 0x00001000, iomemtype);
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sysbus_init_mmio(dev, 0x1000, iomemtype);
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register_savevm("sp804", -1, 1, sp804_save, sp804_load, s);
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register_savevm("sp804", -1, 1, sp804_save, sp804_load, s);
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}
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}
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@ -278,7 +278,8 @@ void sp804_init(uint32_t base, qemu_irq irq)
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/* Integrator/CP timer module. */
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/* Integrator/CP timer module. */
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typedef struct {
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typedef struct {
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void *timer[3];
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SysBusDevice busdev;
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arm_timer_state *timer[3];
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} icp_pit_state;
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} icp_pit_state;
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static uint32_t icp_pit_read(void *opaque, target_phys_addr_t offset)
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static uint32_t icp_pit_read(void *opaque, target_phys_addr_t offset)
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@ -322,21 +323,32 @@ static CPUWriteMemoryFunc *icp_pit_writefn[] = {
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icp_pit_write
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icp_pit_write
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};
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};
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void icp_pit_init(uint32_t base, qemu_irq *pic, int irq)
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static void icp_pit_init(SysBusDevice *dev)
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{
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{
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int iomemtype;
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int iomemtype;
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icp_pit_state *s;
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icp_pit_state *s = FROM_SYSBUS(icp_pit_state, dev);
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s = (icp_pit_state *)qemu_mallocz(sizeof(icp_pit_state));
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/* Timer 0 runs at the system clock speed (40MHz). */
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/* Timer 0 runs at the system clock speed (40MHz). */
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s->timer[0] = arm_timer_init(40000000, pic[irq]);
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s->timer[0] = arm_timer_init(40000000);
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/* The other two timers run at 1MHz. */
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/* The other two timers run at 1MHz. */
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s->timer[1] = arm_timer_init(1000000, pic[irq + 1]);
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s->timer[1] = arm_timer_init(1000000);
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s->timer[2] = arm_timer_init(1000000, pic[irq + 2]);
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s->timer[2] = arm_timer_init(1000000);
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sysbus_init_irq(dev, &s->timer[0]->irq);
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sysbus_init_irq(dev, &s->timer[1]->irq);
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sysbus_init_irq(dev, &s->timer[2]->irq);
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iomemtype = cpu_register_io_memory(0, icp_pit_readfn,
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iomemtype = cpu_register_io_memory(0, icp_pit_readfn,
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icp_pit_writefn, s);
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icp_pit_writefn, s);
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cpu_register_physical_memory(base, 0x00001000, iomemtype);
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sysbus_init_mmio(dev, 0x1000, iomemtype);
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/* This device has no state to save/restore. The component timers will
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/* This device has no state to save/restore. The component timers will
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save themselves. */
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save themselves. */
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}
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}
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static void arm_timer_register_devices(void)
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{
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sysbus_register_dev("integrator_pit", sizeof(icp_pit_state), icp_pit_init);
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sysbus_register_dev("sp804", sizeof(sp804_state), sp804_init);
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}
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device_init(arm_timer_register_devices)
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@ -486,8 +486,9 @@ static void integratorcp_init(ram_addr_t ram_size,
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for (i = 0; i < 32; i++) {
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for (i = 0; i < 32; i++) {
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pic[i] = qdev_get_irq_sink(dev, i);
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pic[i] = qdev_get_irq_sink(dev, i);
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}
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}
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dev = sysbus_create_simple("integrator_pic", 0xca000000, pic[26]);
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sysbus_create_simple("integrator_pic", 0xca000000, pic[26]);
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icp_pit_init(0x13000000, pic, 5);
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sysbus_create_varargs("integrator_pit", 0x13000000,
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pic[5], pic[6], pic[7], NULL);
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sysbus_create_simple("pl031", 0x15000000, pic[8]);
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sysbus_create_simple("pl031", 0x15000000, pic[8]);
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sysbus_create_simple("pl011", 0x16000000, pic[1]);
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sysbus_create_simple("pl011", 0x16000000, pic[1]);
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sysbus_create_simple("pl011", 0x17000000, pic[2]);
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sysbus_create_simple("pl011", 0x17000000, pic[2]);
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@ -26,10 +26,6 @@ qemu_irq *realview_gic_init(uint32_t base, qemu_irq parent_irq);
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/* mpcore.c */
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/* mpcore.c */
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extern qemu_irq *mpcore_irq_init(qemu_irq *cpu_irq);
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extern qemu_irq *mpcore_irq_init(qemu_irq *cpu_irq);
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/* arm-timer.c */
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void sp804_init(uint32_t base, qemu_irq irq);
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void icp_pit_init(uint32_t base, qemu_irq *pic, int irq);
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/* arm_sysctl.c */
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/* arm_sysctl.c */
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void arm_sysctl_init(uint32_t base, uint32_t sys_id);
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void arm_sysctl_init(uint32_t base, uint32_t sys_id);
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@ -91,8 +91,8 @@ static void realview_init(ram_addr_t ram_size,
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/* DMA controller is optional, apparently. */
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/* DMA controller is optional, apparently. */
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pl080_init(0x10030000, pic[24], 2);
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pl080_init(0x10030000, pic[24], 2);
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sp804_init(0x10011000, pic[4]);
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sysbus_create_simple("sp804", 0x10011000, pic[4]);
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sp804_init(0x10012000, pic[5]);
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sysbus_create_simple("sp804", 0x10012000, pic[5]);
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sysbus_create_simple("pl110_versatile", 0x10020000, pic[23]);
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sysbus_create_simple("pl110_versatile", 0x10020000, pic[23]);
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@ -216,8 +216,8 @@ static void versatile_init(ram_addr_t ram_size,
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sysbus_create_simple("pl011", 0x10009000, sic[6]);
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sysbus_create_simple("pl011", 0x10009000, sic[6]);
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pl080_init(0x10130000, pic[17], 8);
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pl080_init(0x10130000, pic[17], 8);
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sp804_init(0x101e2000, pic[4]);
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sysbus_create_simple("sp804", 0x101e2000, pic[4]);
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sp804_init(0x101e3000, pic[5]);
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sysbus_create_simple("sp804", 0x101e3000, pic[5]);
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/* The versatile/PB actually has a modified Color LCD controller
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/* The versatile/PB actually has a modified Color LCD controller
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that includes hardware cursor support from the PL111. */
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that includes hardware cursor support from the PL111. */
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