hw/misc/mps2-scc: Implement changes for AN547
Implement the minor changes required to the SCC block for AN547 images: * CFG2 and CFG5 exist (like AN524) * CFG3 is reserved (like AN524) * CFG0 bit 1 is CPU_WAIT; we don't implement it, but note this in the TODO comment Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210219144617.4782-40-peter.maydell@linaro.org
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@ -110,14 +110,14 @@ static uint64_t mps2_scc_read(void *opaque, hwaddr offset, unsigned size)
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r = s->cfg1;
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break;
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case A_CFG2:
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if (scc_partno(s) != 0x524) {
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if (scc_partno(s) != 0x524 && scc_partno(s) != 0x547) {
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/* CFG2 reserved on other boards */
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goto bad_offset;
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}
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r = s->cfg2;
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break;
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case A_CFG3:
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if (scc_partno(s) == 0x524) {
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if (scc_partno(s) == 0x524 && scc_partno(s) == 0x547) {
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/* CFG3 reserved on AN524 */
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goto bad_offset;
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}
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@ -130,7 +130,7 @@ static uint64_t mps2_scc_read(void *opaque, hwaddr offset, unsigned size)
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r = s->cfg4;
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break;
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case A_CFG5:
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if (scc_partno(s) != 0x524) {
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if (scc_partno(s) != 0x524 && scc_partno(s) != 0x547) {
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/* CFG5 reserved on other boards */
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goto bad_offset;
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}
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@ -185,7 +185,10 @@ static void mps2_scc_write(void *opaque, hwaddr offset, uint64_t value,
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switch (offset) {
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case A_CFG0:
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/* TODO on some boards bit 0 controls RAM remapping */
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/*
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* TODO on some boards bit 0 controls RAM remapping;
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* on others bit 1 is CPU_WAIT.
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*/
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s->cfg0 = value;
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break;
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case A_CFG1:
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@ -195,7 +198,7 @@ static void mps2_scc_write(void *opaque, hwaddr offset, uint64_t value,
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}
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break;
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case A_CFG2:
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if (scc_partno(s) != 0x524) {
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if (scc_partno(s) != 0x524 && scc_partno(s) != 0x547) {
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/* CFG2 reserved on other boards */
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goto bad_offset;
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}
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@ -203,7 +206,7 @@ static void mps2_scc_write(void *opaque, hwaddr offset, uint64_t value,
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s->cfg2 = value;
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break;
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case A_CFG5:
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if (scc_partno(s) != 0x524) {
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if (scc_partno(s) != 0x524 && scc_partno(s) != 0x547) {
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/* CFG5 reserved on other boards */
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goto bad_offset;
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}
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