target-arm queue:
* update libvixl to 1.4 * remove version_minimum_id_old from ARM devices * stellaris_enet tx/rx/migration overhaul * various minor fixes for coverity issues -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.11 (GNU/Linux) iQIcBAABCAAGBQJTcjlYAAoJEDwlJe0UNgze1W0P/3BZSUHqRW/LVTTHUOwSTTAd yBTYcj1pe5nCznmvaW3zXaccGTkB7lvhmVIbW/8fbRjXyZkI5RcLY2p1bhIGEYIl sCmpZ/QlqQyJiK9hHey5jBUVfH/jJFdGAOqxAs42+yGx6NE/UDKC0gNk2N3VRXP4 ctA1IrOlOHGJuTtI6Yht02PJIQllw7n5CnF8UsvwycpyR2jRGG4FTtRX11fvnVxv 6D8HxvjS/sOFrNauviKzqn3gNC5yTOFiWYhLhZt3MNF2QlTexvv6weod8Jqo/evO ZNjAlSjtIDEbu0J2TYmTEY0lT5LOm2TfLedyipMhkQCGULGdsXvPrbOOAe3k5QnS iU5NDMd0nipqA4uvfbQ9nc9Oj+l0EASlsrigQ4AyChjSqoiCRe71jCyNFWtcdBze SIuYOoniwdw+7Eyp7PD80igSdmymeqrjl4qsslMXIry8Uhlm7DJjP2Y6dkvKI+W2 GW5eqtgCeKXbI04yUr4xvxzgHD2LnpQVxuQuQTtY/qabP1YOMB9gDMW3E6d4ttFQ cxvDmyxB/yb3iBXt4QFUWAdoIeRJceHO94WZvAnVRsvumONeQq8W/N/Q9zfIG0GU mFJQ9cab0s+f/Vc7Ri/IIrvK2UlK0ZrKc+wGfXLqTmBKBozAFV+Mw0g21wQrBcY4 YtOkpi68JqtTE0xws5W8 =plIm -----END PGP SIGNATURE----- Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20140513' into staging target-arm queue: * update libvixl to 1.4 * remove version_minimum_id_old from ARM devices * stellaris_enet tx/rx/migration overhaul * various minor fixes for coverity issues # gpg: Signature made Tue 13 May 2014 16:25:12 BST using RSA key ID 14360CDE # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" * remotes/pmaydell/tags/pull-target-arm-20140513: hw/arm/omap_gpmc: Avoid buffer overrun filling prefetch FIFO hw/arm/stellaris: Correct handling of GPTM TAR register hw/timer/exynos4210_mct: Avoid overflow in exynos4210_ltick_recalc_count hw/dma/omap_dma: Add (uint32_t) casts when shifting uint16_t by 16 hw/arm/omap1: Avoid unintended sign extension writing omap_rtc YEARS_REG hw/net/cadence_gem: Remove dead code hw/intc/allwinner-a10-pic: Add missing 'break' target-arm/helper.c: Don't flush the TLB if SCTLR is rewritten unchanged hw/net/stellaris_enet: Convert to vmstate hw/net/stellaris_enet: Get rid of rx_fifo pointer hw/net/stellaris_enet: Fix debug format strings hw/net/stellaris_enet: Correctly implement the TR and THR registers hw/net/stellaris_enet: Rewrite tx fifo handling code hw/net/stellaris_enet: Correct handling of packet padding hw/net/stellaris_enet: Restructure tx_fifo code to avoid buffer overrun savevm: Remove all the unneeded version_minimum_id_old (arm) disas/libvixl: Update to libvixl 1.4 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
commit
6b7aa99eb4
File diff suppressed because it is too large
Load diff
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@ -116,6 +116,8 @@ V_(ImmCmpBranch, 23, 5, SignedBits) \
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V_(ImmLLiteral, 23, 5, SignedBits) \
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V_(ImmLLiteral, 23, 5, SignedBits) \
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V_(ImmException, 20, 5, Bits) \
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V_(ImmException, 20, 5, Bits) \
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V_(ImmHint, 11, 5, Bits) \
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V_(ImmHint, 11, 5, Bits) \
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V_(ImmBarrierDomain, 11, 10, Bits) \
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V_(ImmBarrierType, 9, 8, Bits) \
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\
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\
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/* System (MRS, MSR) */ \
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/* System (MRS, MSR) */ \
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V_(ImmSystemRegister, 19, 5, Bits) \
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V_(ImmSystemRegister, 19, 5, Bits) \
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@ -181,7 +183,7 @@ enum Condition {
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inline Condition InvertCondition(Condition cond) {
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inline Condition InvertCondition(Condition cond) {
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// Conditions al and nv behave identically, as "always true". They can't be
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// Conditions al and nv behave identically, as "always true". They can't be
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// inverted, because there is no "always false" condition.
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// inverted, because there is no "always false" condition.
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ASSERT((cond != al) && (cond != nv));
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VIXL_ASSERT((cond != al) && (cond != nv));
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return static_cast<Condition>(cond ^ 1);
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return static_cast<Condition>(cond ^ 1);
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}
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}
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@ -246,6 +248,20 @@ enum SystemHint {
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SEVL = 5
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SEVL = 5
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};
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};
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enum BarrierDomain {
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OuterShareable = 0,
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NonShareable = 1,
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InnerShareable = 2,
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FullSystem = 3
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};
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enum BarrierType {
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BarrierOther = 0,
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BarrierReads = 1,
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BarrierWrites = 2,
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BarrierAll = 3
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};
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// System/special register names.
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// System/special register names.
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// This information is not encoded as one field but as the concatenation of
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// This information is not encoded as one field but as the concatenation of
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// multiple fields (Op0<0>, Op1, Crn, Crm, Op2).
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// multiple fields (Op0<0>, Op1, Crn, Crm, Op2).
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@ -274,7 +290,7 @@ enum SystemRegister {
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//
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//
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// The enumerations can be used like this:
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// The enumerations can be used like this:
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//
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//
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// ASSERT(instr->Mask(PCRelAddressingFMask) == PCRelAddressingFixed);
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// VIXL_ASSERT(instr->Mask(PCRelAddressingFMask) == PCRelAddressingFixed);
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// switch(instr->Mask(PCRelAddressingMask)) {
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// switch(instr->Mask(PCRelAddressingMask)) {
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// case ADR: Format("adr 'Xd, 'AddrPCRelByte"); break;
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// case ADR: Format("adr 'Xd, 'AddrPCRelByte"); break;
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// case ADRP: Format("adrp 'Xd, 'AddrPCRelPage"); break;
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// case ADRP: Format("adrp 'Xd, 'AddrPCRelPage"); break;
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@ -560,6 +576,15 @@ enum ExceptionOp {
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DCPS3 = ExceptionFixed | 0x00A00003
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DCPS3 = ExceptionFixed | 0x00A00003
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};
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};
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enum MemBarrierOp {
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MemBarrierFixed = 0xD503309F,
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MemBarrierFMask = 0xFFFFF09F,
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MemBarrierMask = 0xFFFFF0FF,
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DSB = MemBarrierFixed | 0x00000000,
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DMB = MemBarrierFixed | 0x00000020,
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ISB = MemBarrierFixed | 0x00000040
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};
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// Any load or store.
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// Any load or store.
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enum LoadStoreAnyOp {
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enum LoadStoreAnyOp {
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LoadStoreAnyFMask = 0x0a000000,
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LoadStoreAnyFMask = 0x0a000000,
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@ -927,17 +952,22 @@ enum FPDataProcessing1SourceOp {
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FRINTN = FRINTN_s,
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FRINTN = FRINTN_s,
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FRINTP_s = FPDataProcessing1SourceFixed | 0x00048000,
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FRINTP_s = FPDataProcessing1SourceFixed | 0x00048000,
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FRINTP_d = FPDataProcessing1SourceFixed | FP64 | 0x00048000,
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FRINTP_d = FPDataProcessing1SourceFixed | FP64 | 0x00048000,
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FRINTP = FRINTP_s,
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FRINTM_s = FPDataProcessing1SourceFixed | 0x00050000,
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FRINTM_s = FPDataProcessing1SourceFixed | 0x00050000,
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FRINTM_d = FPDataProcessing1SourceFixed | FP64 | 0x00050000,
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FRINTM_d = FPDataProcessing1SourceFixed | FP64 | 0x00050000,
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FRINTM = FRINTM_s,
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FRINTZ_s = FPDataProcessing1SourceFixed | 0x00058000,
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FRINTZ_s = FPDataProcessing1SourceFixed | 0x00058000,
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FRINTZ_d = FPDataProcessing1SourceFixed | FP64 | 0x00058000,
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FRINTZ_d = FPDataProcessing1SourceFixed | FP64 | 0x00058000,
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FRINTZ = FRINTZ_s,
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FRINTZ = FRINTZ_s,
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FRINTA_s = FPDataProcessing1SourceFixed | 0x00060000,
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FRINTA_s = FPDataProcessing1SourceFixed | 0x00060000,
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FRINTA_d = FPDataProcessing1SourceFixed | FP64 | 0x00060000,
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FRINTA_d = FPDataProcessing1SourceFixed | FP64 | 0x00060000,
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FRINTA = FRINTA_s,
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FRINTX_s = FPDataProcessing1SourceFixed | 0x00070000,
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FRINTX_s = FPDataProcessing1SourceFixed | 0x00070000,
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FRINTX_d = FPDataProcessing1SourceFixed | FP64 | 0x00070000,
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FRINTX_d = FPDataProcessing1SourceFixed | FP64 | 0x00070000,
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FRINTX = FRINTX_s,
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FRINTI_s = FPDataProcessing1SourceFixed | 0x00078000,
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FRINTI_s = FPDataProcessing1SourceFixed | 0x00078000,
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FRINTI_d = FPDataProcessing1SourceFixed | FP64 | 0x00078000
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FRINTI_d = FPDataProcessing1SourceFixed | FP64 | 0x00078000,
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FRINTI = FRINTI_s
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};
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};
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// Floating point data processing 2 source.
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// Floating point data processing 2 source.
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@ -132,7 +132,7 @@ void Decoder::InsertVisitorBefore(DecoderVisitor* new_visitor,
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}
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}
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// We reached the end of the list. The last element must be
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// We reached the end of the list. The last element must be
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// registered_visitor.
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// registered_visitor.
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ASSERT(*it == registered_visitor);
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VIXL_ASSERT(*it == registered_visitor);
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visitors_.insert(it, new_visitor);
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visitors_.insert(it, new_visitor);
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}
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}
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@ -150,7 +150,7 @@ void Decoder::InsertVisitorAfter(DecoderVisitor* new_visitor,
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}
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}
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// We reached the end of the list. The last element must be
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// We reached the end of the list. The last element must be
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// registered_visitor.
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// registered_visitor.
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ASSERT(*it == registered_visitor);
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VIXL_ASSERT(*it == registered_visitor);
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visitors_.push_back(new_visitor);
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visitors_.push_back(new_visitor);
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}
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}
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@ -161,16 +161,16 @@ void Decoder::RemoveVisitor(DecoderVisitor* visitor) {
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void Decoder::DecodePCRelAddressing(Instruction* instr) {
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void Decoder::DecodePCRelAddressing(Instruction* instr) {
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ASSERT(instr->Bits(27, 24) == 0x0);
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VIXL_ASSERT(instr->Bits(27, 24) == 0x0);
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// We know bit 28 is set, as <b28:b27> = 0 is filtered out at the top level
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// We know bit 28 is set, as <b28:b27> = 0 is filtered out at the top level
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// decode.
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// decode.
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ASSERT(instr->Bit(28) == 0x1);
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VIXL_ASSERT(instr->Bit(28) == 0x1);
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VisitPCRelAddressing(instr);
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VisitPCRelAddressing(instr);
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}
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}
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void Decoder::DecodeBranchSystemException(Instruction* instr) {
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void Decoder::DecodeBranchSystemException(Instruction* instr) {
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ASSERT((instr->Bits(27, 24) == 0x4) ||
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VIXL_ASSERT((instr->Bits(27, 24) == 0x4) ||
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(instr->Bits(27, 24) == 0x5) ||
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(instr->Bits(27, 24) == 0x5) ||
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(instr->Bits(27, 24) == 0x6) ||
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(instr->Bits(27, 24) == 0x6) ||
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(instr->Bits(27, 24) == 0x7) );
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(instr->Bits(27, 24) == 0x7) );
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@ -271,7 +271,7 @@ void Decoder::DecodeBranchSystemException(Instruction* instr) {
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void Decoder::DecodeLoadStore(Instruction* instr) {
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void Decoder::DecodeLoadStore(Instruction* instr) {
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ASSERT((instr->Bits(27, 24) == 0x8) ||
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VIXL_ASSERT((instr->Bits(27, 24) == 0x8) ||
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(instr->Bits(27, 24) == 0x9) ||
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(instr->Bits(27, 24) == 0x9) ||
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(instr->Bits(27, 24) == 0xC) ||
|
(instr->Bits(27, 24) == 0xC) ||
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(instr->Bits(27, 24) == 0xD) );
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(instr->Bits(27, 24) == 0xD) );
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@ -390,7 +390,7 @@ void Decoder::DecodeLoadStore(Instruction* instr) {
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void Decoder::DecodeLogical(Instruction* instr) {
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void Decoder::DecodeLogical(Instruction* instr) {
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ASSERT(instr->Bits(27, 24) == 0x2);
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VIXL_ASSERT(instr->Bits(27, 24) == 0x2);
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|
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if (instr->Mask(0x80400000) == 0x00400000) {
|
if (instr->Mask(0x80400000) == 0x00400000) {
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VisitUnallocated(instr);
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VisitUnallocated(instr);
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@ -409,7 +409,7 @@ void Decoder::DecodeLogical(Instruction* instr) {
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|
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void Decoder::DecodeBitfieldExtract(Instruction* instr) {
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void Decoder::DecodeBitfieldExtract(Instruction* instr) {
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ASSERT(instr->Bits(27, 24) == 0x3);
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VIXL_ASSERT(instr->Bits(27, 24) == 0x3);
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|
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if ((instr->Mask(0x80400000) == 0x80000000) ||
|
if ((instr->Mask(0x80400000) == 0x80000000) ||
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(instr->Mask(0x80400000) == 0x00400000) ||
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(instr->Mask(0x80400000) == 0x00400000) ||
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@ -434,7 +434,7 @@ void Decoder::DecodeBitfieldExtract(Instruction* instr) {
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|
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|
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void Decoder::DecodeAddSubImmediate(Instruction* instr) {
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void Decoder::DecodeAddSubImmediate(Instruction* instr) {
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ASSERT(instr->Bits(27, 24) == 0x1);
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VIXL_ASSERT(instr->Bits(27, 24) == 0x1);
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if (instr->Bit(23) == 1) {
|
if (instr->Bit(23) == 1) {
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VisitUnallocated(instr);
|
VisitUnallocated(instr);
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} else {
|
} else {
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|
@ -444,8 +444,8 @@ void Decoder::DecodeAddSubImmediate(Instruction* instr) {
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|
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||||||
|
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void Decoder::DecodeDataProcessing(Instruction* instr) {
|
void Decoder::DecodeDataProcessing(Instruction* instr) {
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ASSERT((instr->Bits(27, 24) == 0xA) ||
|
VIXL_ASSERT((instr->Bits(27, 24) == 0xA) ||
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||||||
(instr->Bits(27, 24) == 0xB) );
|
(instr->Bits(27, 24) == 0xB));
|
||||||
|
|
||||||
if (instr->Bit(24) == 0) {
|
if (instr->Bit(24) == 0) {
|
||||||
if (instr->Bit(28) == 0) {
|
if (instr->Bit(28) == 0) {
|
||||||
|
@ -559,8 +559,8 @@ void Decoder::DecodeDataProcessing(Instruction* instr) {
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||||||
|
|
||||||
|
|
||||||
void Decoder::DecodeFP(Instruction* instr) {
|
void Decoder::DecodeFP(Instruction* instr) {
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||||||
ASSERT((instr->Bits(27, 24) == 0xE) ||
|
VIXL_ASSERT((instr->Bits(27, 24) == 0xE) ||
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||||||
(instr->Bits(27, 24) == 0xF) );
|
(instr->Bits(27, 24) == 0xF));
|
||||||
|
|
||||||
if (instr->Bit(28) == 0) {
|
if (instr->Bit(28) == 0) {
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||||||
DecodeAdvSIMDDataProcessing(instr);
|
DecodeAdvSIMDDataProcessing(instr);
|
||||||
|
@ -665,14 +665,14 @@ void Decoder::DecodeFP(Instruction* instr) {
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||||||
VisitFPConditionalSelect(instr);
|
VisitFPConditionalSelect(instr);
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||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
default: UNREACHABLE();
|
default: VIXL_UNREACHABLE();
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
} else {
|
} else {
|
||||||
// Bit 30 == 1 has been handled earlier.
|
// Bit 30 == 1 has been handled earlier.
|
||||||
ASSERT(instr->Bit(30) == 0);
|
VIXL_ASSERT(instr->Bit(30) == 0);
|
||||||
if (instr->Mask(0xA0800000) != 0) {
|
if (instr->Mask(0xA0800000) != 0) {
|
||||||
VisitUnallocated(instr);
|
VisitUnallocated(instr);
|
||||||
} else {
|
} else {
|
||||||
|
@ -687,21 +687,21 @@ void Decoder::DecodeFP(Instruction* instr) {
|
||||||
|
|
||||||
void Decoder::DecodeAdvSIMDLoadStore(Instruction* instr) {
|
void Decoder::DecodeAdvSIMDLoadStore(Instruction* instr) {
|
||||||
// TODO: Implement Advanced SIMD load/store instruction decode.
|
// TODO: Implement Advanced SIMD load/store instruction decode.
|
||||||
ASSERT(instr->Bits(29, 25) == 0x6);
|
VIXL_ASSERT(instr->Bits(29, 25) == 0x6);
|
||||||
VisitUnimplemented(instr);
|
VisitUnimplemented(instr);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
void Decoder::DecodeAdvSIMDDataProcessing(Instruction* instr) {
|
void Decoder::DecodeAdvSIMDDataProcessing(Instruction* instr) {
|
||||||
// TODO: Implement Advanced SIMD data processing instruction decode.
|
// TODO: Implement Advanced SIMD data processing instruction decode.
|
||||||
ASSERT(instr->Bits(27, 25) == 0x7);
|
VIXL_ASSERT(instr->Bits(27, 25) == 0x7);
|
||||||
VisitUnimplemented(instr);
|
VisitUnimplemented(instr);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
#define DEFINE_VISITOR_CALLERS(A) \
|
#define DEFINE_VISITOR_CALLERS(A) \
|
||||||
void Decoder::Visit##A(Instruction *instr) { \
|
void Decoder::Visit##A(Instruction *instr) { \
|
||||||
ASSERT(instr->Mask(A##FMask) == A##Fixed); \
|
VIXL_ASSERT(instr->Mask(A##FMask) == A##Fixed); \
|
||||||
std::list<DecoderVisitor*>::iterator it; \
|
std::list<DecoderVisitor*>::iterator it; \
|
||||||
for (it = visitors_.begin(); it != visitors_.end(); it++) { \
|
for (it = visitors_.begin(); it != visitors_.end(); it++) { \
|
||||||
(*it)->Visit##A(instr); \
|
(*it)->Visit##A(instr); \
|
||||||
|
|
|
@ -95,7 +95,7 @@ void Disassembler::VisitAddSubImmediate(Instruction* instr) {
|
||||||
}
|
}
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
default: UNREACHABLE();
|
default: VIXL_UNREACHABLE();
|
||||||
}
|
}
|
||||||
Format(instr, mnemonic, form);
|
Format(instr, mnemonic, form);
|
||||||
}
|
}
|
||||||
|
@ -142,7 +142,7 @@ void Disassembler::VisitAddSubShifted(Instruction* instr) {
|
||||||
}
|
}
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
default: UNREACHABLE();
|
default: VIXL_UNREACHABLE();
|
||||||
}
|
}
|
||||||
Format(instr, mnemonic, form);
|
Format(instr, mnemonic, form);
|
||||||
}
|
}
|
||||||
|
@ -180,7 +180,7 @@ void Disassembler::VisitAddSubExtended(Instruction* instr) {
|
||||||
}
|
}
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
default: UNREACHABLE();
|
default: VIXL_UNREACHABLE();
|
||||||
}
|
}
|
||||||
Format(instr, mnemonic, form);
|
Format(instr, mnemonic, form);
|
||||||
}
|
}
|
||||||
|
@ -215,7 +215,7 @@ void Disassembler::VisitAddSubWithCarry(Instruction* instr) {
|
||||||
}
|
}
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
default: UNREACHABLE();
|
default: VIXL_UNREACHABLE();
|
||||||
}
|
}
|
||||||
Format(instr, mnemonic, form);
|
Format(instr, mnemonic, form);
|
||||||
}
|
}
|
||||||
|
@ -258,30 +258,30 @@ void Disassembler::VisitLogicalImmediate(Instruction* instr) {
|
||||||
}
|
}
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
default: UNREACHABLE();
|
default: VIXL_UNREACHABLE();
|
||||||
}
|
}
|
||||||
Format(instr, mnemonic, form);
|
Format(instr, mnemonic, form);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
bool Disassembler::IsMovzMovnImm(unsigned reg_size, uint64_t value) {
|
bool Disassembler::IsMovzMovnImm(unsigned reg_size, uint64_t value) {
|
||||||
ASSERT((reg_size == kXRegSize) ||
|
VIXL_ASSERT((reg_size == kXRegSize) ||
|
||||||
((reg_size == kWRegSize) && (value <= 0xffffffff)));
|
((reg_size == kWRegSize) && (value <= 0xffffffff)));
|
||||||
|
|
||||||
// Test for movz: 16 bits set at positions 0, 16, 32 or 48.
|
// Test for movz: 16 bits set at positions 0, 16, 32 or 48.
|
||||||
if (((value & 0xffffffffffff0000ULL) == 0ULL) ||
|
if (((value & UINT64_C(0xffffffffffff0000)) == 0) ||
|
||||||
((value & 0xffffffff0000ffffULL) == 0ULL) ||
|
((value & UINT64_C(0xffffffff0000ffff)) == 0) ||
|
||||||
((value & 0xffff0000ffffffffULL) == 0ULL) ||
|
((value & UINT64_C(0xffff0000ffffffff)) == 0) ||
|
||||||
((value & 0x0000ffffffffffffULL) == 0ULL)) {
|
((value & UINT64_C(0x0000ffffffffffff)) == 0)) {
|
||||||
return true;
|
return true;
|
||||||
}
|
}
|
||||||
|
|
||||||
// Test for movn: NOT(16 bits set at positions 0, 16, 32 or 48).
|
// Test for movn: NOT(16 bits set at positions 0, 16, 32 or 48).
|
||||||
if ((reg_size == kXRegSize) &&
|
if ((reg_size == kXRegSize) &&
|
||||||
(((value & 0xffffffffffff0000ULL) == 0xffffffffffff0000ULL) ||
|
(((~value & UINT64_C(0xffffffffffff0000)) == 0) ||
|
||||||
((value & 0xffffffff0000ffffULL) == 0xffffffff0000ffffULL) ||
|
((~value & UINT64_C(0xffffffff0000ffff)) == 0) ||
|
||||||
((value & 0xffff0000ffffffffULL) == 0xffff0000ffffffffULL) ||
|
((~value & UINT64_C(0xffff0000ffffffff)) == 0) ||
|
||||||
((value & 0x0000ffffffffffffULL) == 0x0000ffffffffffffULL))) {
|
((~value & UINT64_C(0x0000ffffffffffff)) == 0))) {
|
||||||
return true;
|
return true;
|
||||||
}
|
}
|
||||||
if ((reg_size == kWRegSize) &&
|
if ((reg_size == kWRegSize) &&
|
||||||
|
@ -337,7 +337,7 @@ void Disassembler::VisitLogicalShifted(Instruction* instr) {
|
||||||
}
|
}
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
default: UNREACHABLE();
|
default: VIXL_UNREACHABLE();
|
||||||
}
|
}
|
||||||
|
|
||||||
Format(instr, mnemonic, form);
|
Format(instr, mnemonic, form);
|
||||||
|
@ -353,7 +353,7 @@ void Disassembler::VisitConditionalCompareRegister(Instruction* instr) {
|
||||||
case CCMN_x: mnemonic = "ccmn"; break;
|
case CCMN_x: mnemonic = "ccmn"; break;
|
||||||
case CCMP_w:
|
case CCMP_w:
|
||||||
case CCMP_x: mnemonic = "ccmp"; break;
|
case CCMP_x: mnemonic = "ccmp"; break;
|
||||||
default: UNREACHABLE();
|
default: VIXL_UNREACHABLE();
|
||||||
}
|
}
|
||||||
Format(instr, mnemonic, form);
|
Format(instr, mnemonic, form);
|
||||||
}
|
}
|
||||||
|
@ -368,7 +368,7 @@ void Disassembler::VisitConditionalCompareImmediate(Instruction* instr) {
|
||||||
case CCMN_x_imm: mnemonic = "ccmn"; break;
|
case CCMN_x_imm: mnemonic = "ccmn"; break;
|
||||||
case CCMP_w_imm:
|
case CCMP_w_imm:
|
||||||
case CCMP_x_imm: mnemonic = "ccmp"; break;
|
case CCMP_x_imm: mnemonic = "ccmp"; break;
|
||||||
default: UNREACHABLE();
|
default: VIXL_UNREACHABLE();
|
||||||
}
|
}
|
||||||
Format(instr, mnemonic, form);
|
Format(instr, mnemonic, form);
|
||||||
}
|
}
|
||||||
|
@ -421,7 +421,7 @@ void Disassembler::VisitConditionalSelect(Instruction* instr) {
|
||||||
}
|
}
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
default: UNREACHABLE();
|
default: VIXL_UNREACHABLE();
|
||||||
}
|
}
|
||||||
Format(instr, mnemonic, form);
|
Format(instr, mnemonic, form);
|
||||||
}
|
}
|
||||||
|
@ -520,7 +520,7 @@ void Disassembler::VisitExtract(Instruction* instr) {
|
||||||
}
|
}
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
default: UNREACHABLE();
|
default: VIXL_UNREACHABLE();
|
||||||
}
|
}
|
||||||
Format(instr, mnemonic, form);
|
Format(instr, mnemonic, form);
|
||||||
}
|
}
|
||||||
|
@ -538,7 +538,7 @@ void Disassembler::VisitPCRelAddressing(Instruction* instr) {
|
||||||
void Disassembler::VisitConditionalBranch(Instruction* instr) {
|
void Disassembler::VisitConditionalBranch(Instruction* instr) {
|
||||||
switch (instr->Mask(ConditionalBranchMask)) {
|
switch (instr->Mask(ConditionalBranchMask)) {
|
||||||
case B_cond: Format(instr, "b.'CBrn", "'BImmCond"); break;
|
case B_cond: Format(instr, "b.'CBrn", "'BImmCond"); break;
|
||||||
default: UNREACHABLE();
|
default: VIXL_UNREACHABLE();
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -570,7 +570,7 @@ void Disassembler::VisitUnconditionalBranch(Instruction* instr) {
|
||||||
switch (instr->Mask(UnconditionalBranchMask)) {
|
switch (instr->Mask(UnconditionalBranchMask)) {
|
||||||
case B: mnemonic = "b"; break;
|
case B: mnemonic = "b"; break;
|
||||||
case BL: mnemonic = "bl"; break;
|
case BL: mnemonic = "bl"; break;
|
||||||
default: UNREACHABLE();
|
default: VIXL_UNREACHABLE();
|
||||||
}
|
}
|
||||||
Format(instr, mnemonic, form);
|
Format(instr, mnemonic, form);
|
||||||
}
|
}
|
||||||
|
@ -591,7 +591,7 @@ void Disassembler::VisitDataProcessing1Source(Instruction* instr) {
|
||||||
FORMAT(CLS, "cls");
|
FORMAT(CLS, "cls");
|
||||||
#undef FORMAT
|
#undef FORMAT
|
||||||
case REV32_x: mnemonic = "rev32"; break;
|
case REV32_x: mnemonic = "rev32"; break;
|
||||||
default: UNREACHABLE();
|
default: VIXL_UNREACHABLE();
|
||||||
}
|
}
|
||||||
Format(instr, mnemonic, form);
|
Format(instr, mnemonic, form);
|
||||||
}
|
}
|
||||||
|
@ -690,7 +690,7 @@ void Disassembler::VisitDataProcessing3Source(Instruction* instr) {
|
||||||
form = form_xxx;
|
form = form_xxx;
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
default: UNREACHABLE();
|
default: VIXL_UNREACHABLE();
|
||||||
}
|
}
|
||||||
Format(instr, mnemonic, form);
|
Format(instr, mnemonic, form);
|
||||||
}
|
}
|
||||||
|
@ -705,7 +705,7 @@ void Disassembler::VisitCompareBranch(Instruction* instr) {
|
||||||
case CBZ_x: mnemonic = "cbz"; break;
|
case CBZ_x: mnemonic = "cbz"; break;
|
||||||
case CBNZ_w:
|
case CBNZ_w:
|
||||||
case CBNZ_x: mnemonic = "cbnz"; break;
|
case CBNZ_x: mnemonic = "cbnz"; break;
|
||||||
default: UNREACHABLE();
|
default: VIXL_UNREACHABLE();
|
||||||
}
|
}
|
||||||
Format(instr, mnemonic, form);
|
Format(instr, mnemonic, form);
|
||||||
}
|
}
|
||||||
|
@ -722,7 +722,7 @@ void Disassembler::VisitTestBranch(Instruction* instr) {
|
||||||
switch (instr->Mask(TestBranchMask)) {
|
switch (instr->Mask(TestBranchMask)) {
|
||||||
case TBZ: mnemonic = "tbz"; break;
|
case TBZ: mnemonic = "tbz"; break;
|
||||||
case TBNZ: mnemonic = "tbnz"; break;
|
case TBNZ: mnemonic = "tbnz"; break;
|
||||||
default: UNREACHABLE();
|
default: VIXL_UNREACHABLE();
|
||||||
}
|
}
|
||||||
Format(instr, mnemonic, form);
|
Format(instr, mnemonic, form);
|
||||||
}
|
}
|
||||||
|
@ -742,7 +742,7 @@ void Disassembler::VisitMoveWideImmediate(Instruction* instr) {
|
||||||
case MOVZ_x: mnemonic = "movz"; break;
|
case MOVZ_x: mnemonic = "movz"; break;
|
||||||
case MOVK_w:
|
case MOVK_w:
|
||||||
case MOVK_x: mnemonic = "movk"; form = "'Rd, 'IMoveLSL"; break;
|
case MOVK_x: mnemonic = "movk"; form = "'Rd, 'IMoveLSL"; break;
|
||||||
default: UNREACHABLE();
|
default: VIXL_UNREACHABLE();
|
||||||
}
|
}
|
||||||
Format(instr, mnemonic, form);
|
Format(instr, mnemonic, form);
|
||||||
}
|
}
|
||||||
|
@ -981,7 +981,7 @@ void Disassembler::VisitFPConditionalSelect(Instruction* instr) {
|
||||||
switch (instr->Mask(FPConditionalSelectMask)) {
|
switch (instr->Mask(FPConditionalSelectMask)) {
|
||||||
case FCSEL_s:
|
case FCSEL_s:
|
||||||
case FCSEL_d: mnemonic = "fcsel"; break;
|
case FCSEL_d: mnemonic = "fcsel"; break;
|
||||||
default: UNREACHABLE();
|
default: VIXL_UNREACHABLE();
|
||||||
}
|
}
|
||||||
Format(instr, mnemonic, form);
|
Format(instr, mnemonic, form);
|
||||||
}
|
}
|
||||||
|
@ -1033,7 +1033,7 @@ void Disassembler::VisitFPDataProcessing2Source(Instruction* instr) {
|
||||||
FORMAT(FMINNM, "fminnm");
|
FORMAT(FMINNM, "fminnm");
|
||||||
FORMAT(FNMUL, "fnmul");
|
FORMAT(FNMUL, "fnmul");
|
||||||
#undef FORMAT
|
#undef FORMAT
|
||||||
default: UNREACHABLE();
|
default: VIXL_UNREACHABLE();
|
||||||
}
|
}
|
||||||
Format(instr, mnemonic, form);
|
Format(instr, mnemonic, form);
|
||||||
}
|
}
|
||||||
|
@ -1052,7 +1052,7 @@ void Disassembler::VisitFPDataProcessing3Source(Instruction* instr) {
|
||||||
FORMAT(FNMADD, "fnmadd");
|
FORMAT(FNMADD, "fnmadd");
|
||||||
FORMAT(FNMSUB, "fnmsub");
|
FORMAT(FNMSUB, "fnmsub");
|
||||||
#undef FORMAT
|
#undef FORMAT
|
||||||
default: UNREACHABLE();
|
default: VIXL_UNREACHABLE();
|
||||||
}
|
}
|
||||||
Format(instr, mnemonic, form);
|
Format(instr, mnemonic, form);
|
||||||
}
|
}
|
||||||
|
@ -1065,7 +1065,7 @@ void Disassembler::VisitFPImmediate(Instruction* instr) {
|
||||||
switch (instr->Mask(FPImmediateMask)) {
|
switch (instr->Mask(FPImmediateMask)) {
|
||||||
case FMOV_s_imm: mnemonic = "fmov"; form = "'Sd, 'IFPSingle"; break;
|
case FMOV_s_imm: mnemonic = "fmov"; form = "'Sd, 'IFPSingle"; break;
|
||||||
case FMOV_d_imm: mnemonic = "fmov"; form = "'Dd, 'IFPDouble"; break;
|
case FMOV_d_imm: mnemonic = "fmov"; form = "'Dd, 'IFPDouble"; break;
|
||||||
default: UNREACHABLE();
|
default: VIXL_UNREACHABLE();
|
||||||
}
|
}
|
||||||
Format(instr, mnemonic, form);
|
Format(instr, mnemonic, form);
|
||||||
}
|
}
|
||||||
|
@ -1082,6 +1082,14 @@ void Disassembler::VisitFPIntegerConvert(Instruction* instr) {
|
||||||
case FMOV_xd: mnemonic = "fmov"; form = form_rf; break;
|
case FMOV_xd: mnemonic = "fmov"; form = form_rf; break;
|
||||||
case FMOV_sw:
|
case FMOV_sw:
|
||||||
case FMOV_dx: mnemonic = "fmov"; form = form_fr; break;
|
case FMOV_dx: mnemonic = "fmov"; form = form_fr; break;
|
||||||
|
case FCVTAS_ws:
|
||||||
|
case FCVTAS_xs:
|
||||||
|
case FCVTAS_wd:
|
||||||
|
case FCVTAS_xd: mnemonic = "fcvtas"; form = form_rf; break;
|
||||||
|
case FCVTAU_ws:
|
||||||
|
case FCVTAU_xs:
|
||||||
|
case FCVTAU_wd:
|
||||||
|
case FCVTAU_xd: mnemonic = "fcvtau"; form = form_rf; break;
|
||||||
case FCVTMS_ws:
|
case FCVTMS_ws:
|
||||||
case FCVTMS_xs:
|
case FCVTMS_xs:
|
||||||
case FCVTMS_wd:
|
case FCVTMS_wd:
|
||||||
|
@ -1141,7 +1149,7 @@ void Disassembler::VisitFPFixedPointConvert(Instruction* instr) {
|
||||||
case UCVTF_sx_fixed:
|
case UCVTF_sx_fixed:
|
||||||
case UCVTF_dw_fixed:
|
case UCVTF_dw_fixed:
|
||||||
case UCVTF_dx_fixed: mnemonic = "ucvtf"; form = form_fr; break;
|
case UCVTF_dx_fixed: mnemonic = "ucvtf"; form = form_fr; break;
|
||||||
default: UNREACHABLE();
|
default: VIXL_UNREACHABLE();
|
||||||
}
|
}
|
||||||
Format(instr, mnemonic, form);
|
Format(instr, mnemonic, form);
|
||||||
}
|
}
|
||||||
|
@ -1176,7 +1184,7 @@ void Disassembler::VisitSystem(Instruction* instr) {
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
} else if (instr->Mask(SystemHintFMask) == SystemHintFixed) {
|
} else if (instr->Mask(SystemHintFMask) == SystemHintFixed) {
|
||||||
ASSERT(instr->Mask(SystemHintMask) == HINT);
|
VIXL_ASSERT(instr->Mask(SystemHintMask) == HINT);
|
||||||
switch (instr->ImmHint()) {
|
switch (instr->ImmHint()) {
|
||||||
case NOP: {
|
case NOP: {
|
||||||
mnemonic = "nop";
|
mnemonic = "nop";
|
||||||
|
@ -1184,6 +1192,24 @@ void Disassembler::VisitSystem(Instruction* instr) {
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
} else if (instr->Mask(MemBarrierFMask) == MemBarrierFixed) {
|
||||||
|
switch (instr->Mask(MemBarrierMask)) {
|
||||||
|
case DMB: {
|
||||||
|
mnemonic = "dmb";
|
||||||
|
form = "'M";
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
case DSB: {
|
||||||
|
mnemonic = "dsb";
|
||||||
|
form = "'M";
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
case ISB: {
|
||||||
|
mnemonic = "isb";
|
||||||
|
form = NULL;
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
Format(instr, mnemonic, form);
|
Format(instr, mnemonic, form);
|
||||||
|
@ -1226,7 +1252,7 @@ void Disassembler::ProcessOutput(Instruction* /*instr*/) {
|
||||||
|
|
||||||
void Disassembler::Format(Instruction* instr, const char* mnemonic,
|
void Disassembler::Format(Instruction* instr, const char* mnemonic,
|
||||||
const char* format) {
|
const char* format) {
|
||||||
ASSERT(mnemonic != NULL);
|
VIXL_ASSERT(mnemonic != NULL);
|
||||||
ResetOutput();
|
ResetOutput();
|
||||||
Substitute(instr, mnemonic);
|
Substitute(instr, mnemonic);
|
||||||
if (format != NULL) {
|
if (format != NULL) {
|
||||||
|
@ -1268,8 +1294,9 @@ int Disassembler::SubstituteField(Instruction* instr, const char* format) {
|
||||||
case 'A': return SubstitutePCRelAddressField(instr, format);
|
case 'A': return SubstitutePCRelAddressField(instr, format);
|
||||||
case 'B': return SubstituteBranchTargetField(instr, format);
|
case 'B': return SubstituteBranchTargetField(instr, format);
|
||||||
case 'O': return SubstituteLSRegOffsetField(instr, format);
|
case 'O': return SubstituteLSRegOffsetField(instr, format);
|
||||||
|
case 'M': return SubstituteBarrierField(instr, format);
|
||||||
default: {
|
default: {
|
||||||
UNREACHABLE();
|
VIXL_UNREACHABLE();
|
||||||
return 1;
|
return 1;
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
@ -1294,7 +1321,7 @@ int Disassembler::SubstituteRegisterField(Instruction* instr,
|
||||||
}
|
}
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
default: UNREACHABLE();
|
default: VIXL_UNREACHABLE();
|
||||||
}
|
}
|
||||||
|
|
||||||
// Increase field length for registers tagged as stack.
|
// Increase field length for registers tagged as stack.
|
||||||
|
@ -1331,7 +1358,7 @@ int Disassembler::SubstituteRegisterField(Instruction* instr,
|
||||||
|
|
||||||
int Disassembler::SubstituteImmediateField(Instruction* instr,
|
int Disassembler::SubstituteImmediateField(Instruction* instr,
|
||||||
const char* format) {
|
const char* format) {
|
||||||
ASSERT(format[0] == 'I');
|
VIXL_ASSERT(format[0] == 'I');
|
||||||
|
|
||||||
switch (format[1]) {
|
switch (format[1]) {
|
||||||
case 'M': { // IMoveImm or IMoveLSL.
|
case 'M': { // IMoveImm or IMoveLSL.
|
||||||
|
@ -1339,10 +1366,10 @@ int Disassembler::SubstituteImmediateField(Instruction* instr,
|
||||||
uint64_t imm = instr->ImmMoveWide() << (16 * instr->ShiftMoveWide());
|
uint64_t imm = instr->ImmMoveWide() << (16 * instr->ShiftMoveWide());
|
||||||
AppendToOutput("#0x%" PRIx64, imm);
|
AppendToOutput("#0x%" PRIx64, imm);
|
||||||
} else {
|
} else {
|
||||||
ASSERT(format[5] == 'L');
|
VIXL_ASSERT(format[5] == 'L');
|
||||||
AppendToOutput("#0x%" PRIx64, instr->ImmMoveWide());
|
AppendToOutput("#0x%" PRIx64, instr->ImmMoveWide());
|
||||||
if (instr->ShiftMoveWide() > 0) {
|
if (instr->ShiftMoveWide() > 0) {
|
||||||
AppendToOutput(", lsl #%" PRId64, 16 * instr->ShiftMoveWide());
|
AppendToOutput(", lsl #%d", 16 * instr->ShiftMoveWide());
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
return 8;
|
return 8;
|
||||||
|
@ -1384,14 +1411,14 @@ int Disassembler::SubstituteImmediateField(Instruction* instr,
|
||||||
return 6;
|
return 6;
|
||||||
}
|
}
|
||||||
case 'A': { // IAddSub.
|
case 'A': { // IAddSub.
|
||||||
ASSERT(instr->ShiftAddSub() <= 1);
|
VIXL_ASSERT(instr->ShiftAddSub() <= 1);
|
||||||
int64_t imm = instr->ImmAddSub() << (12 * instr->ShiftAddSub());
|
int64_t imm = instr->ImmAddSub() << (12 * instr->ShiftAddSub());
|
||||||
AppendToOutput("#0x%" PRIx64 " (%" PRId64 ")", imm, imm);
|
AppendToOutput("#0x%" PRIx64 " (%" PRId64 ")", imm, imm);
|
||||||
return 7;
|
return 7;
|
||||||
}
|
}
|
||||||
case 'F': { // IFPSingle, IFPDouble or IFPFBits.
|
case 'F': { // IFPSingle, IFPDouble or IFPFBits.
|
||||||
if (format[3] == 'F') { // IFPFbits.
|
if (format[3] == 'F') { // IFPFbits.
|
||||||
AppendToOutput("#%" PRId64, 64 - instr->FPScale());
|
AppendToOutput("#%d", 64 - instr->FPScale());
|
||||||
return 8;
|
return 8;
|
||||||
} else {
|
} else {
|
||||||
AppendToOutput("#0x%" PRIx64 " (%.4f)", instr->ImmFP(),
|
AppendToOutput("#0x%" PRIx64 " (%.4f)", instr->ImmFP(),
|
||||||
|
@ -1412,27 +1439,27 @@ int Disassembler::SubstituteImmediateField(Instruction* instr,
|
||||||
return 5;
|
return 5;
|
||||||
}
|
}
|
||||||
case 'P': { // IP - Conditional compare.
|
case 'P': { // IP - Conditional compare.
|
||||||
AppendToOutput("#%" PRId64, instr->ImmCondCmp());
|
AppendToOutput("#%d", instr->ImmCondCmp());
|
||||||
return 2;
|
return 2;
|
||||||
}
|
}
|
||||||
case 'B': { // Bitfields.
|
case 'B': { // Bitfields.
|
||||||
return SubstituteBitfieldImmediateField(instr, format);
|
return SubstituteBitfieldImmediateField(instr, format);
|
||||||
}
|
}
|
||||||
case 'E': { // IExtract.
|
case 'E': { // IExtract.
|
||||||
AppendToOutput("#%" PRId64, instr->ImmS());
|
AppendToOutput("#%d", instr->ImmS());
|
||||||
return 8;
|
return 8;
|
||||||
}
|
}
|
||||||
case 'S': { // IS - Test and branch bit.
|
case 'S': { // IS - Test and branch bit.
|
||||||
AppendToOutput("#%" PRId64, (instr->ImmTestBranchBit5() << 5) |
|
AppendToOutput("#%d", (instr->ImmTestBranchBit5() << 5) |
|
||||||
instr->ImmTestBranchBit40());
|
instr->ImmTestBranchBit40());
|
||||||
return 2;
|
return 2;
|
||||||
}
|
}
|
||||||
case 'D': { // IDebug - HLT and BRK instructions.
|
case 'D': { // IDebug - HLT and BRK instructions.
|
||||||
AppendToOutput("#0x%" PRIx64, instr->ImmException());
|
AppendToOutput("#0x%x", instr->ImmException());
|
||||||
return 6;
|
return 6;
|
||||||
}
|
}
|
||||||
default: {
|
default: {
|
||||||
UNIMPLEMENTED();
|
VIXL_UNIMPLEMENTED();
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
@ -1441,7 +1468,7 @@ int Disassembler::SubstituteImmediateField(Instruction* instr,
|
||||||
|
|
||||||
int Disassembler::SubstituteBitfieldImmediateField(Instruction* instr,
|
int Disassembler::SubstituteBitfieldImmediateField(Instruction* instr,
|
||||||
const char* format) {
|
const char* format) {
|
||||||
ASSERT((format[0] == 'I') && (format[1] == 'B'));
|
VIXL_ASSERT((format[0] == 'I') && (format[1] == 'B'));
|
||||||
unsigned r = instr->ImmR();
|
unsigned r = instr->ImmR();
|
||||||
unsigned s = instr->ImmS();
|
unsigned s = instr->ImmS();
|
||||||
|
|
||||||
|
@ -1455,19 +1482,19 @@ int Disassembler::SubstituteBitfieldImmediateField(Instruction* instr,
|
||||||
AppendToOutput("#%d", s + 1);
|
AppendToOutput("#%d", s + 1);
|
||||||
return 5;
|
return 5;
|
||||||
} else {
|
} else {
|
||||||
ASSERT(format[3] == '-');
|
VIXL_ASSERT(format[3] == '-');
|
||||||
AppendToOutput("#%d", s - r + 1);
|
AppendToOutput("#%d", s - r + 1);
|
||||||
return 7;
|
return 7;
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
case 'Z': { // IBZ-r.
|
case 'Z': { // IBZ-r.
|
||||||
ASSERT((format[3] == '-') && (format[4] == 'r'));
|
VIXL_ASSERT((format[3] == '-') && (format[4] == 'r'));
|
||||||
unsigned reg_size = (instr->SixtyFourBits() == 1) ? kXRegSize : kWRegSize;
|
unsigned reg_size = (instr->SixtyFourBits() == 1) ? kXRegSize : kWRegSize;
|
||||||
AppendToOutput("#%d", reg_size - r);
|
AppendToOutput("#%d", reg_size - r);
|
||||||
return 5;
|
return 5;
|
||||||
}
|
}
|
||||||
default: {
|
default: {
|
||||||
UNREACHABLE();
|
VIXL_UNREACHABLE();
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
@ -1476,7 +1503,7 @@ int Disassembler::SubstituteBitfieldImmediateField(Instruction* instr,
|
||||||
|
|
||||||
int Disassembler::SubstituteLiteralField(Instruction* instr,
|
int Disassembler::SubstituteLiteralField(Instruction* instr,
|
||||||
const char* format) {
|
const char* format) {
|
||||||
ASSERT(strncmp(format, "LValue", 6) == 0);
|
VIXL_ASSERT(strncmp(format, "LValue", 6) == 0);
|
||||||
USE(format);
|
USE(format);
|
||||||
|
|
||||||
switch (instr->Mask(LoadLiteralMask)) {
|
switch (instr->Mask(LoadLiteralMask)) {
|
||||||
|
@ -1484,7 +1511,7 @@ int Disassembler::SubstituteLiteralField(Instruction* instr,
|
||||||
case LDR_x_lit:
|
case LDR_x_lit:
|
||||||
case LDR_s_lit:
|
case LDR_s_lit:
|
||||||
case LDR_d_lit: AppendToOutput("(addr %p)", instr->LiteralAddress()); break;
|
case LDR_d_lit: AppendToOutput("(addr %p)", instr->LiteralAddress()); break;
|
||||||
default: UNREACHABLE();
|
default: VIXL_UNREACHABLE();
|
||||||
}
|
}
|
||||||
|
|
||||||
return 6;
|
return 6;
|
||||||
|
@ -1492,12 +1519,12 @@ int Disassembler::SubstituteLiteralField(Instruction* instr,
|
||||||
|
|
||||||
|
|
||||||
int Disassembler::SubstituteShiftField(Instruction* instr, const char* format) {
|
int Disassembler::SubstituteShiftField(Instruction* instr, const char* format) {
|
||||||
ASSERT(format[0] == 'H');
|
VIXL_ASSERT(format[0] == 'H');
|
||||||
ASSERT(instr->ShiftDP() <= 0x3);
|
VIXL_ASSERT(instr->ShiftDP() <= 0x3);
|
||||||
|
|
||||||
switch (format[1]) {
|
switch (format[1]) {
|
||||||
case 'D': { // HDP.
|
case 'D': { // HDP.
|
||||||
ASSERT(instr->ShiftDP() != ROR);
|
VIXL_ASSERT(instr->ShiftDP() != ROR);
|
||||||
} // Fall through.
|
} // Fall through.
|
||||||
case 'L': { // HLo.
|
case 'L': { // HLo.
|
||||||
if (instr->ImmDPShift() != 0) {
|
if (instr->ImmDPShift() != 0) {
|
||||||
|
@ -1508,7 +1535,7 @@ int Disassembler::SubstituteShiftField(Instruction* instr, const char* format) {
|
||||||
return 3;
|
return 3;
|
||||||
}
|
}
|
||||||
default:
|
default:
|
||||||
UNIMPLEMENTED();
|
VIXL_UNIMPLEMENTED();
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
@ -1516,7 +1543,7 @@ int Disassembler::SubstituteShiftField(Instruction* instr, const char* format) {
|
||||||
|
|
||||||
int Disassembler::SubstituteConditionField(Instruction* instr,
|
int Disassembler::SubstituteConditionField(Instruction* instr,
|
||||||
const char* format) {
|
const char* format) {
|
||||||
ASSERT(format[0] == 'C');
|
VIXL_ASSERT(format[0] == 'C');
|
||||||
const char* condition_code[] = { "eq", "ne", "hs", "lo",
|
const char* condition_code[] = { "eq", "ne", "hs", "lo",
|
||||||
"mi", "pl", "vs", "vc",
|
"mi", "pl", "vs", "vc",
|
||||||
"hi", "ls", "ge", "lt",
|
"hi", "ls", "ge", "lt",
|
||||||
|
@ -1538,27 +1565,27 @@ int Disassembler::SubstituteConditionField(Instruction* instr,
|
||||||
int Disassembler::SubstitutePCRelAddressField(Instruction* instr,
|
int Disassembler::SubstitutePCRelAddressField(Instruction* instr,
|
||||||
const char* format) {
|
const char* format) {
|
||||||
USE(format);
|
USE(format);
|
||||||
ASSERT(strncmp(format, "AddrPCRel", 9) == 0);
|
VIXL_ASSERT(strncmp(format, "AddrPCRel", 9) == 0);
|
||||||
|
|
||||||
int offset = instr->ImmPCRel();
|
int offset = instr->ImmPCRel();
|
||||||
|
|
||||||
// Only ADR (AddrPCRelByte) is supported.
|
// Only ADR (AddrPCRelByte) is supported.
|
||||||
ASSERT(strcmp(format, "AddrPCRelByte") == 0);
|
VIXL_ASSERT(strcmp(format, "AddrPCRelByte") == 0);
|
||||||
|
|
||||||
char sign = '+';
|
char sign = '+';
|
||||||
if (offset < 0) {
|
if (offset < 0) {
|
||||||
offset = -offset;
|
offset = -offset;
|
||||||
sign = '-';
|
sign = '-';
|
||||||
}
|
}
|
||||||
// TODO: Extend this to support printing the target address.
|
VIXL_STATIC_ASSERT(sizeof(*instr) == 1);
|
||||||
AppendToOutput("#%c0x%x", sign, offset);
|
AppendToOutput("#%c0x%x (addr %p)", sign, offset, instr + offset);
|
||||||
return 13;
|
return 13;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
int Disassembler::SubstituteBranchTargetField(Instruction* instr,
|
int Disassembler::SubstituteBranchTargetField(Instruction* instr,
|
||||||
const char* format) {
|
const char* format) {
|
||||||
ASSERT(strncmp(format, "BImm", 4) == 0);
|
VIXL_ASSERT(strncmp(format, "BImm", 4) == 0);
|
||||||
|
|
||||||
int64_t offset = 0;
|
int64_t offset = 0;
|
||||||
switch (format[5]) {
|
switch (format[5]) {
|
||||||
|
@ -1570,7 +1597,7 @@ int Disassembler::SubstituteBranchTargetField(Instruction* instr,
|
||||||
case 'm': offset = instr->ImmCmpBranch(); break;
|
case 'm': offset = instr->ImmCmpBranch(); break;
|
||||||
// BImmTest - test and branch immediate.
|
// BImmTest - test and branch immediate.
|
||||||
case 'e': offset = instr->ImmTestBranch(); break;
|
case 'e': offset = instr->ImmTestBranch(); break;
|
||||||
default: UNIMPLEMENTED();
|
default: VIXL_UNIMPLEMENTED();
|
||||||
}
|
}
|
||||||
offset <<= kInstructionSizeLog2;
|
offset <<= kInstructionSizeLog2;
|
||||||
char sign = '+';
|
char sign = '+';
|
||||||
|
@ -1578,15 +1605,16 @@ int Disassembler::SubstituteBranchTargetField(Instruction* instr,
|
||||||
offset = -offset;
|
offset = -offset;
|
||||||
sign = '-';
|
sign = '-';
|
||||||
}
|
}
|
||||||
AppendToOutput("#%c0x%" PRIx64, sign, offset);
|
VIXL_STATIC_ASSERT(sizeof(*instr) == 1);
|
||||||
|
AppendToOutput("#%c0x%" PRIx64 " (addr %p)", sign, offset, instr + offset);
|
||||||
return 8;
|
return 8;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
int Disassembler::SubstituteExtendField(Instruction* instr,
|
int Disassembler::SubstituteExtendField(Instruction* instr,
|
||||||
const char* format) {
|
const char* format) {
|
||||||
ASSERT(strncmp(format, "Ext", 3) == 0);
|
VIXL_ASSERT(strncmp(format, "Ext", 3) == 0);
|
||||||
ASSERT(instr->ExtendMode() <= 7);
|
VIXL_ASSERT(instr->ExtendMode() <= 7);
|
||||||
USE(format);
|
USE(format);
|
||||||
|
|
||||||
const char* extend_mode[] = { "uxtb", "uxth", "uxtw", "uxtx",
|
const char* extend_mode[] = { "uxtb", "uxth", "uxtw", "uxtx",
|
||||||
|
@ -1598,12 +1626,12 @@ int Disassembler::SubstituteExtendField(Instruction* instr,
|
||||||
(((instr->ExtendMode() == UXTW) && (instr->SixtyFourBits() == 0)) ||
|
(((instr->ExtendMode() == UXTW) && (instr->SixtyFourBits() == 0)) ||
|
||||||
(instr->ExtendMode() == UXTX))) {
|
(instr->ExtendMode() == UXTX))) {
|
||||||
if (instr->ImmExtendShift() > 0) {
|
if (instr->ImmExtendShift() > 0) {
|
||||||
AppendToOutput(", lsl #%" PRId64, instr->ImmExtendShift());
|
AppendToOutput(", lsl #%d", instr->ImmExtendShift());
|
||||||
}
|
}
|
||||||
} else {
|
} else {
|
||||||
AppendToOutput(", %s", extend_mode[instr->ExtendMode()]);
|
AppendToOutput(", %s", extend_mode[instr->ExtendMode()]);
|
||||||
if (instr->ImmExtendShift() > 0) {
|
if (instr->ImmExtendShift() > 0) {
|
||||||
AppendToOutput(" #%" PRId64, instr->ImmExtendShift());
|
AppendToOutput(" #%d", instr->ImmExtendShift());
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
return 3;
|
return 3;
|
||||||
|
@ -1612,7 +1640,7 @@ int Disassembler::SubstituteExtendField(Instruction* instr,
|
||||||
|
|
||||||
int Disassembler::SubstituteLSRegOffsetField(Instruction* instr,
|
int Disassembler::SubstituteLSRegOffsetField(Instruction* instr,
|
||||||
const char* format) {
|
const char* format) {
|
||||||
ASSERT(strncmp(format, "Offsetreg", 9) == 0);
|
VIXL_ASSERT(strncmp(format, "Offsetreg", 9) == 0);
|
||||||
const char* extend_mode[] = { "undefined", "undefined", "uxtw", "lsl",
|
const char* extend_mode[] = { "undefined", "undefined", "uxtw", "lsl",
|
||||||
"undefined", "undefined", "sxtw", "sxtx" };
|
"undefined", "undefined", "sxtw", "sxtx" };
|
||||||
USE(format);
|
USE(format);
|
||||||
|
@ -1632,7 +1660,7 @@ int Disassembler::SubstituteLSRegOffsetField(Instruction* instr,
|
||||||
if (!((ext == UXTX) && (shift == 0))) {
|
if (!((ext == UXTX) && (shift == 0))) {
|
||||||
AppendToOutput(", %s", extend_mode[ext]);
|
AppendToOutput(", %s", extend_mode[ext]);
|
||||||
if (shift != 0) {
|
if (shift != 0) {
|
||||||
AppendToOutput(" #%" PRId64, instr->SizeLS());
|
AppendToOutput(" #%d", instr->SizeLS());
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
return 9;
|
return 9;
|
||||||
|
@ -1641,7 +1669,7 @@ int Disassembler::SubstituteLSRegOffsetField(Instruction* instr,
|
||||||
|
|
||||||
int Disassembler::SubstitutePrefetchField(Instruction* instr,
|
int Disassembler::SubstitutePrefetchField(Instruction* instr,
|
||||||
const char* format) {
|
const char* format) {
|
||||||
ASSERT(format[0] == 'P');
|
VIXL_ASSERT(format[0] == 'P');
|
||||||
USE(format);
|
USE(format);
|
||||||
|
|
||||||
int prefetch_mode = instr->PrefetchMode();
|
int prefetch_mode = instr->PrefetchMode();
|
||||||
|
@ -1654,6 +1682,23 @@ int Disassembler::SubstitutePrefetchField(Instruction* instr,
|
||||||
return 6;
|
return 6;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
int Disassembler::SubstituteBarrierField(Instruction* instr,
|
||||||
|
const char* format) {
|
||||||
|
VIXL_ASSERT(format[0] == 'M');
|
||||||
|
USE(format);
|
||||||
|
|
||||||
|
static const char* options[4][4] = {
|
||||||
|
{ "sy (0b0000)", "oshld", "oshst", "osh" },
|
||||||
|
{ "sy (0b0100)", "nshld", "nshst", "nsh" },
|
||||||
|
{ "sy (0b1000)", "ishld", "ishst", "ish" },
|
||||||
|
{ "sy (0b1100)", "ld", "st", "sy" }
|
||||||
|
};
|
||||||
|
int domain = instr->ImmBarrierDomain();
|
||||||
|
int type = instr->ImmBarrierType();
|
||||||
|
|
||||||
|
AppendToOutput("%s", options[domain][type]);
|
||||||
|
return 1;
|
||||||
|
}
|
||||||
|
|
||||||
void Disassembler::ResetOutput() {
|
void Disassembler::ResetOutput() {
|
||||||
buffer_pos_ = 0;
|
buffer_pos_ = 0;
|
||||||
|
|
|
@ -64,6 +64,7 @@ class Disassembler: public DecoderVisitor {
|
||||||
int SubstituteBranchTargetField(Instruction* instr, const char* format);
|
int SubstituteBranchTargetField(Instruction* instr, const char* format);
|
||||||
int SubstituteLSRegOffsetField(Instruction* instr, const char* format);
|
int SubstituteLSRegOffsetField(Instruction* instr, const char* format);
|
||||||
int SubstitutePrefetchField(Instruction* instr, const char* format);
|
int SubstitutePrefetchField(Instruction* instr, const char* format);
|
||||||
|
int SubstituteBarrierField(Instruction* instr, const char* format);
|
||||||
|
|
||||||
inline bool RdIsZROrSP(Instruction* instr) const {
|
inline bool RdIsZROrSP(Instruction* instr) const {
|
||||||
return (instr->Rd() == kZeroRegCode);
|
return (instr->Rd() == kZeroRegCode);
|
||||||
|
|
|
@ -33,20 +33,20 @@ namespace vixl {
|
||||||
static uint64_t RotateRight(uint64_t value,
|
static uint64_t RotateRight(uint64_t value,
|
||||||
unsigned int rotate,
|
unsigned int rotate,
|
||||||
unsigned int width) {
|
unsigned int width) {
|
||||||
ASSERT(width <= 64);
|
VIXL_ASSERT(width <= 64);
|
||||||
rotate &= 63;
|
rotate &= 63;
|
||||||
return ((value & ((1UL << rotate) - 1UL)) << (width - rotate)) |
|
return ((value & ((UINT64_C(1) << rotate) - 1)) <<
|
||||||
(value >> rotate);
|
(width - rotate)) | (value >> rotate);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
static uint64_t RepeatBitsAcrossReg(unsigned reg_size,
|
static uint64_t RepeatBitsAcrossReg(unsigned reg_size,
|
||||||
uint64_t value,
|
uint64_t value,
|
||||||
unsigned width) {
|
unsigned width) {
|
||||||
ASSERT((width == 2) || (width == 4) || (width == 8) || (width == 16) ||
|
VIXL_ASSERT((width == 2) || (width == 4) || (width == 8) || (width == 16) ||
|
||||||
(width == 32));
|
(width == 32));
|
||||||
ASSERT((reg_size == kWRegSize) || (reg_size == kXRegSize));
|
VIXL_ASSERT((reg_size == kWRegSize) || (reg_size == kXRegSize));
|
||||||
uint64_t result = value & ((1UL << width) - 1UL);
|
uint64_t result = value & ((UINT64_C(1) << width) - 1);
|
||||||
for (unsigned i = width; i < reg_size; i *= 2) {
|
for (unsigned i = width; i < reg_size; i *= 2) {
|
||||||
result |= (result << i);
|
result |= (result << i);
|
||||||
}
|
}
|
||||||
|
@ -84,7 +84,7 @@ uint64_t Instruction::ImmLogical() {
|
||||||
if (imm_s == 0x3F) {
|
if (imm_s == 0x3F) {
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
uint64_t bits = (1UL << (imm_s + 1)) - 1;
|
uint64_t bits = (UINT64_C(1) << (imm_s + 1)) - 1;
|
||||||
return RotateRight(bits, imm_r, 64);
|
return RotateRight(bits, imm_r, 64);
|
||||||
} else {
|
} else {
|
||||||
if ((imm_s >> 1) == 0x1F) {
|
if ((imm_s >> 1) == 0x1F) {
|
||||||
|
@ -96,14 +96,14 @@ uint64_t Instruction::ImmLogical() {
|
||||||
if ((imm_s & mask) == mask) {
|
if ((imm_s & mask) == mask) {
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
uint64_t bits = (1UL << ((imm_s & mask) + 1)) - 1;
|
uint64_t bits = (UINT64_C(1) << ((imm_s & mask) + 1)) - 1;
|
||||||
return RepeatBitsAcrossReg(reg_size,
|
return RepeatBitsAcrossReg(reg_size,
|
||||||
RotateRight(bits, imm_r & mask, width),
|
RotateRight(bits, imm_r & mask, width),
|
||||||
width);
|
width);
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
UNREACHABLE();
|
VIXL_UNREACHABLE();
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -155,7 +155,7 @@ Instruction* Instruction::ImmPCOffsetTarget() {
|
||||||
offset = ImmPCRel();
|
offset = ImmPCRel();
|
||||||
} else {
|
} else {
|
||||||
// All PC-relative branches.
|
// All PC-relative branches.
|
||||||
ASSERT(BranchType() != UnknownBranchType);
|
VIXL_ASSERT(BranchType() != UnknownBranchType);
|
||||||
// Relative branch offsets are instruction-size-aligned.
|
// Relative branch offsets are instruction-size-aligned.
|
||||||
offset = ImmBranch() << kInstructionSizeLog2;
|
offset = ImmBranch() << kInstructionSizeLog2;
|
||||||
}
|
}
|
||||||
|
@ -169,7 +169,7 @@ inline int Instruction::ImmBranch() const {
|
||||||
case UncondBranchType: return ImmUncondBranch();
|
case UncondBranchType: return ImmUncondBranch();
|
||||||
case CompareBranchType: return ImmCmpBranch();
|
case CompareBranchType: return ImmCmpBranch();
|
||||||
case TestBranchType: return ImmTestBranch();
|
case TestBranchType: return ImmTestBranch();
|
||||||
default: UNREACHABLE();
|
default: VIXL_UNREACHABLE();
|
||||||
}
|
}
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
@ -186,7 +186,7 @@ void Instruction::SetImmPCOffsetTarget(Instruction* target) {
|
||||||
|
|
||||||
void Instruction::SetPCRelImmTarget(Instruction* target) {
|
void Instruction::SetPCRelImmTarget(Instruction* target) {
|
||||||
// ADRP is not supported, so 'this' must point to an ADR instruction.
|
// ADRP is not supported, so 'this' must point to an ADR instruction.
|
||||||
ASSERT(Mask(PCRelAddressingMask) == ADR);
|
VIXL_ASSERT(Mask(PCRelAddressingMask) == ADR);
|
||||||
|
|
||||||
Instr imm = Assembler::ImmPCRelAddress(target - this);
|
Instr imm = Assembler::ImmPCRelAddress(target - this);
|
||||||
|
|
||||||
|
@ -195,7 +195,7 @@ void Instruction::SetPCRelImmTarget(Instruction* target) {
|
||||||
|
|
||||||
|
|
||||||
void Instruction::SetBranchImmTarget(Instruction* target) {
|
void Instruction::SetBranchImmTarget(Instruction* target) {
|
||||||
ASSERT(((target - this) & 3) == 0);
|
VIXL_ASSERT(((target - this) & 3) == 0);
|
||||||
Instr branch_imm = 0;
|
Instr branch_imm = 0;
|
||||||
uint32_t imm_mask = 0;
|
uint32_t imm_mask = 0;
|
||||||
int offset = (target - this) >> kInstructionSizeLog2;
|
int offset = (target - this) >> kInstructionSizeLog2;
|
||||||
|
@ -220,14 +220,14 @@ void Instruction::SetBranchImmTarget(Instruction* target) {
|
||||||
imm_mask = ImmTestBranch_mask;
|
imm_mask = ImmTestBranch_mask;
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
default: UNREACHABLE();
|
default: VIXL_UNREACHABLE();
|
||||||
}
|
}
|
||||||
SetInstructionBits(Mask(~imm_mask) | branch_imm);
|
SetInstructionBits(Mask(~imm_mask) | branch_imm);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
void Instruction::SetImmLLiteral(Instruction* source) {
|
void Instruction::SetImmLLiteral(Instruction* source) {
|
||||||
ASSERT(((source - this) & 3) == 0);
|
VIXL_ASSERT(((source - this) & 3) == 0);
|
||||||
int offset = (source - this) >> kLiteralEntrySizeLog2;
|
int offset = (source - this) >> kLiteralEntrySizeLog2;
|
||||||
Instr imm = Assembler::ImmLLiteral(offset);
|
Instr imm = Assembler::ImmLLiteral(offset);
|
||||||
Instr mask = ImmLLiteral_mask;
|
Instr mask = ImmLLiteral_mask;
|
||||||
|
|
|
@ -44,30 +44,36 @@ const unsigned kMaxLoadLiteralRange = 1 * MBytes;
|
||||||
const unsigned kWRegSize = 32;
|
const unsigned kWRegSize = 32;
|
||||||
const unsigned kWRegSizeLog2 = 5;
|
const unsigned kWRegSizeLog2 = 5;
|
||||||
const unsigned kWRegSizeInBytes = kWRegSize / 8;
|
const unsigned kWRegSizeInBytes = kWRegSize / 8;
|
||||||
|
const unsigned kWRegSizeInBytesLog2 = kWRegSizeLog2 - 3;
|
||||||
const unsigned kXRegSize = 64;
|
const unsigned kXRegSize = 64;
|
||||||
const unsigned kXRegSizeLog2 = 6;
|
const unsigned kXRegSizeLog2 = 6;
|
||||||
const unsigned kXRegSizeInBytes = kXRegSize / 8;
|
const unsigned kXRegSizeInBytes = kXRegSize / 8;
|
||||||
|
const unsigned kXRegSizeInBytesLog2 = kXRegSizeLog2 - 3;
|
||||||
const unsigned kSRegSize = 32;
|
const unsigned kSRegSize = 32;
|
||||||
const unsigned kSRegSizeLog2 = 5;
|
const unsigned kSRegSizeLog2 = 5;
|
||||||
const unsigned kSRegSizeInBytes = kSRegSize / 8;
|
const unsigned kSRegSizeInBytes = kSRegSize / 8;
|
||||||
|
const unsigned kSRegSizeInBytesLog2 = kSRegSizeLog2 - 3;
|
||||||
const unsigned kDRegSize = 64;
|
const unsigned kDRegSize = 64;
|
||||||
const unsigned kDRegSizeLog2 = 6;
|
const unsigned kDRegSizeLog2 = 6;
|
||||||
const unsigned kDRegSizeInBytes = kDRegSize / 8;
|
const unsigned kDRegSizeInBytes = kDRegSize / 8;
|
||||||
const int64_t kWRegMask = 0x00000000ffffffffLL;
|
const unsigned kDRegSizeInBytesLog2 = kDRegSizeLog2 - 3;
|
||||||
const int64_t kXRegMask = 0xffffffffffffffffLL;
|
const uint64_t kWRegMask = UINT64_C(0xffffffff);
|
||||||
const int64_t kSRegMask = 0x00000000ffffffffLL;
|
const uint64_t kXRegMask = UINT64_C(0xffffffffffffffff);
|
||||||
const int64_t kDRegMask = 0xffffffffffffffffLL;
|
const uint64_t kSRegMask = UINT64_C(0xffffffff);
|
||||||
const int64_t kXSignMask = 0x1LL << 63;
|
const uint64_t kDRegMask = UINT64_C(0xffffffffffffffff);
|
||||||
const int64_t kWSignMask = 0x1LL << 31;
|
const uint64_t kSSignMask = UINT64_C(0x80000000);
|
||||||
const int64_t kByteMask = 0xffL;
|
const uint64_t kDSignMask = UINT64_C(0x8000000000000000);
|
||||||
const int64_t kHalfWordMask = 0xffffL;
|
const uint64_t kWSignMask = UINT64_C(0x80000000);
|
||||||
const int64_t kWordMask = 0xffffffffLL;
|
const uint64_t kXSignMask = UINT64_C(0x8000000000000000);
|
||||||
const uint64_t kXMaxUInt = 0xffffffffffffffffULL;
|
const uint64_t kByteMask = UINT64_C(0xff);
|
||||||
const uint64_t kWMaxUInt = 0xffffffffULL;
|
const uint64_t kHalfWordMask = UINT64_C(0xffff);
|
||||||
const int64_t kXMaxInt = 0x7fffffffffffffffLL;
|
const uint64_t kWordMask = UINT64_C(0xffffffff);
|
||||||
const int64_t kXMinInt = 0x8000000000000000LL;
|
const uint64_t kXMaxUInt = UINT64_C(0xffffffffffffffff);
|
||||||
const int32_t kWMaxInt = 0x7fffffff;
|
const uint64_t kWMaxUInt = UINT64_C(0xffffffff);
|
||||||
const int32_t kWMinInt = 0x80000000;
|
const int64_t kXMaxInt = INT64_C(0x7fffffffffffffff);
|
||||||
|
const int64_t kXMinInt = INT64_C(0x8000000000000000);
|
||||||
|
const int32_t kWMaxInt = INT32_C(0x7fffffff);
|
||||||
|
const int32_t kWMinInt = INT32_C(0x80000000);
|
||||||
const unsigned kLinkRegCode = 30;
|
const unsigned kLinkRegCode = 30;
|
||||||
const unsigned kZeroRegCode = 31;
|
const unsigned kZeroRegCode = 31;
|
||||||
const unsigned kSPRegInternalCode = 63;
|
const unsigned kSPRegInternalCode = 63;
|
||||||
|
@ -81,18 +87,28 @@ const unsigned kFloatExponentBits = 8;
|
||||||
|
|
||||||
const float kFP32PositiveInfinity = rawbits_to_float(0x7f800000);
|
const float kFP32PositiveInfinity = rawbits_to_float(0x7f800000);
|
||||||
const float kFP32NegativeInfinity = rawbits_to_float(0xff800000);
|
const float kFP32NegativeInfinity = rawbits_to_float(0xff800000);
|
||||||
const double kFP64PositiveInfinity = rawbits_to_double(0x7ff0000000000000ULL);
|
const double kFP64PositiveInfinity =
|
||||||
const double kFP64NegativeInfinity = rawbits_to_double(0xfff0000000000000ULL);
|
rawbits_to_double(UINT64_C(0x7ff0000000000000));
|
||||||
|
const double kFP64NegativeInfinity =
|
||||||
|
rawbits_to_double(UINT64_C(0xfff0000000000000));
|
||||||
|
|
||||||
// This value is a signalling NaN as both a double and as a float (taking the
|
// This value is a signalling NaN as both a double and as a float (taking the
|
||||||
// least-significant word).
|
// least-significant word).
|
||||||
static const double kFP64SignallingNaN = rawbits_to_double(0x7ff000007f800001ULL);
|
static const double kFP64SignallingNaN =
|
||||||
|
rawbits_to_double(UINT64_C(0x7ff000007f800001));
|
||||||
static const float kFP32SignallingNaN = rawbits_to_float(0x7f800001);
|
static const float kFP32SignallingNaN = rawbits_to_float(0x7f800001);
|
||||||
|
|
||||||
// A similar value, but as a quiet NaN.
|
// A similar value, but as a quiet NaN.
|
||||||
static const double kFP64QuietNaN = rawbits_to_double(0x7ff800007fc00001ULL);
|
static const double kFP64QuietNaN =
|
||||||
|
rawbits_to_double(UINT64_C(0x7ff800007fc00001));
|
||||||
static const float kFP32QuietNaN = rawbits_to_float(0x7fc00001);
|
static const float kFP32QuietNaN = rawbits_to_float(0x7fc00001);
|
||||||
|
|
||||||
|
// The default NaN values (for FPCR.DN=1).
|
||||||
|
static const double kFP64DefaultNaN =
|
||||||
|
rawbits_to_double(UINT64_C(0x7ff8000000000000));
|
||||||
|
static const float kFP32DefaultNaN = rawbits_to_float(0x7fc00000);
|
||||||
|
|
||||||
|
|
||||||
enum LSDataSize {
|
enum LSDataSize {
|
||||||
LSByte = 0,
|
LSByte = 0,
|
||||||
LSHalfword = 1,
|
LSHalfword = 1,
|
||||||
|
@ -325,7 +341,7 @@ class Instruction {
|
||||||
}
|
}
|
||||||
|
|
||||||
inline Instruction* InstructionAtOffset(int64_t offset) {
|
inline Instruction* InstructionAtOffset(int64_t offset) {
|
||||||
ASSERT(IsWordAligned(this + offset));
|
VIXL_ASSERT(IsWordAligned(this + offset));
|
||||||
return this + offset;
|
return this + offset;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
|
@ -27,8 +27,20 @@
|
||||||
#ifndef VIXL_GLOBALS_H
|
#ifndef VIXL_GLOBALS_H
|
||||||
#define VIXL_GLOBALS_H
|
#define VIXL_GLOBALS_H
|
||||||
|
|
||||||
// Get the standard printf format macros for C99 stdint types.
|
// Get standard C99 macros for integer types.
|
||||||
|
#ifndef __STDC_CONSTANT_MACROS
|
||||||
|
#define __STDC_CONSTANT_MACROS
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifndef __STDC_LIMIT_MACROS
|
||||||
|
#define __STDC_LIMIT_MACROS
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifndef __STDC_FORMAT_MACROS
|
||||||
#define __STDC_FORMAT_MACROS
|
#define __STDC_FORMAT_MACROS
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#include <stdint.h>
|
||||||
#include <inttypes.h>
|
#include <inttypes.h>
|
||||||
|
|
||||||
#include <assert.h>
|
#include <assert.h>
|
||||||
|
@ -45,21 +57,29 @@ typedef uint8_t byte;
|
||||||
const int KBytes = 1024;
|
const int KBytes = 1024;
|
||||||
const int MBytes = 1024 * KBytes;
|
const int MBytes = 1024 * KBytes;
|
||||||
|
|
||||||
#define ABORT() printf("in %s, line %i", __FILE__, __LINE__); abort()
|
#define VIXL_ABORT() printf("in %s, line %i", __FILE__, __LINE__); abort()
|
||||||
#ifdef DEBUG
|
#ifdef DEBUG
|
||||||
#define ASSERT(condition) assert(condition)
|
#define VIXL_ASSERT(condition) assert(condition)
|
||||||
#define CHECK(condition) ASSERT(condition)
|
#define VIXL_CHECK(condition) VIXL_ASSERT(condition)
|
||||||
#define UNIMPLEMENTED() printf("UNIMPLEMENTED\t"); ABORT()
|
#define VIXL_UNIMPLEMENTED() printf("UNIMPLEMENTED\t"); VIXL_ABORT()
|
||||||
#define UNREACHABLE() printf("UNREACHABLE\t"); ABORT()
|
#define VIXL_UNREACHABLE() printf("UNREACHABLE\t"); VIXL_ABORT()
|
||||||
#else
|
#else
|
||||||
#define ASSERT(condition) ((void) 0)
|
#define VIXL_ASSERT(condition) ((void) 0)
|
||||||
#define CHECK(condition) assert(condition)
|
#define VIXL_CHECK(condition) assert(condition)
|
||||||
#define UNIMPLEMENTED() ((void) 0)
|
#define VIXL_UNIMPLEMENTED() ((void) 0)
|
||||||
#define UNREACHABLE() ((void) 0)
|
#define VIXL_UNREACHABLE() ((void) 0)
|
||||||
#endif
|
#endif
|
||||||
|
// This is not as powerful as template based assertions, but it is simple.
|
||||||
|
// It assumes that the descriptions are unique. If this starts being a problem,
|
||||||
|
// we can switch to a different implemention.
|
||||||
|
#define VIXL_CONCAT(a, b) a##b
|
||||||
|
#define VIXL_STATIC_ASSERT_LINE(line, condition) \
|
||||||
|
typedef char VIXL_CONCAT(STATIC_ASSERT_LINE_, line)[(condition) ? 1 : -1] \
|
||||||
|
__attribute__((unused))
|
||||||
|
#define VIXL_STATIC_ASSERT(condition) VIXL_STATIC_ASSERT_LINE(__LINE__, condition) //NOLINT
|
||||||
|
|
||||||
template <typename T> inline void USE(T) {}
|
template <typename T> inline void USE(T) {}
|
||||||
|
|
||||||
#define ALIGNMENT_EXCEPTION() printf("ALIGNMENT EXCEPTION\t"); ABORT()
|
#define VIXL_ALIGNMENT_EXCEPTION() printf("ALIGNMENT EXCEPTION\t"); VIXL_ABORT()
|
||||||
|
|
||||||
#endif // VIXL_GLOBALS_H
|
#endif // VIXL_GLOBALS_H
|
||||||
|
|
|
@ -34,9 +34,7 @@ namespace vixl {
|
||||||
// Currently we assume running the simulator implies running on x86 hardware.
|
// Currently we assume running the simulator implies running on x86 hardware.
|
||||||
inline void HostBreakpoint() { asm("int3"); }
|
inline void HostBreakpoint() { asm("int3"); }
|
||||||
#else
|
#else
|
||||||
inline void HostBreakpoint() {
|
inline void HostBreakpoint() { asm("brk"); }
|
||||||
// TODO: Implement HostBreakpoint on a64.
|
|
||||||
}
|
|
||||||
#endif
|
#endif
|
||||||
} // namespace vixl
|
} // namespace vixl
|
||||||
|
|
||||||
|
|
|
@ -58,9 +58,9 @@ double rawbits_to_double(uint64_t bits) {
|
||||||
|
|
||||||
|
|
||||||
int CountLeadingZeros(uint64_t value, int width) {
|
int CountLeadingZeros(uint64_t value, int width) {
|
||||||
ASSERT((width == 32) || (width == 64));
|
VIXL_ASSERT((width == 32) || (width == 64));
|
||||||
int count = 0;
|
int count = 0;
|
||||||
uint64_t bit_test = 1UL << (width - 1);
|
uint64_t bit_test = UINT64_C(1) << (width - 1);
|
||||||
while ((count < width) && ((bit_test & value) == 0)) {
|
while ((count < width) && ((bit_test & value) == 0)) {
|
||||||
count++;
|
count++;
|
||||||
bit_test >>= 1;
|
bit_test >>= 1;
|
||||||
|
@ -70,7 +70,7 @@ int CountLeadingZeros(uint64_t value, int width) {
|
||||||
|
|
||||||
|
|
||||||
int CountLeadingSignBits(int64_t value, int width) {
|
int CountLeadingSignBits(int64_t value, int width) {
|
||||||
ASSERT((width == 32) || (width == 64));
|
VIXL_ASSERT((width == 32) || (width == 64));
|
||||||
if (value >= 0) {
|
if (value >= 0) {
|
||||||
return CountLeadingZeros(value, width) - 1;
|
return CountLeadingZeros(value, width) - 1;
|
||||||
} else {
|
} else {
|
||||||
|
@ -80,7 +80,7 @@ int CountLeadingSignBits(int64_t value, int width) {
|
||||||
|
|
||||||
|
|
||||||
int CountTrailingZeros(uint64_t value, int width) {
|
int CountTrailingZeros(uint64_t value, int width) {
|
||||||
ASSERT((width == 32) || (width == 64));
|
VIXL_ASSERT((width == 32) || (width == 64));
|
||||||
int count = 0;
|
int count = 0;
|
||||||
while ((count < width) && (((value >> count) & 1) == 0)) {
|
while ((count < width) && (((value >> count) & 1) == 0)) {
|
||||||
count++;
|
count++;
|
||||||
|
@ -92,10 +92,10 @@ int CountTrailingZeros(uint64_t value, int width) {
|
||||||
int CountSetBits(uint64_t value, int width) {
|
int CountSetBits(uint64_t value, int width) {
|
||||||
// TODO: Other widths could be added here, as the implementation already
|
// TODO: Other widths could be added here, as the implementation already
|
||||||
// supports them.
|
// supports them.
|
||||||
ASSERT((width == 32) || (width == 64));
|
VIXL_ASSERT((width == 32) || (width == 64));
|
||||||
|
|
||||||
// Mask out unused bits to ensure that they are not counted.
|
// Mask out unused bits to ensure that they are not counted.
|
||||||
value &= (0xffffffffffffffffULL >> (64-width));
|
value &= (UINT64_C(0xffffffffffffffff) >> (64-width));
|
||||||
|
|
||||||
// Add up the set bits.
|
// Add up the set bits.
|
||||||
// The algorithm works by adding pairs of bit fields together iteratively,
|
// The algorithm works by adding pairs of bit fields together iteratively,
|
||||||
|
@ -108,18 +108,19 @@ int CountSetBits(uint64_t value, int width) {
|
||||||
// value = h+g+f+e d+c+b+a
|
// value = h+g+f+e d+c+b+a
|
||||||
// \ |
|
// \ |
|
||||||
// value = h+g+f+e+d+c+b+a
|
// value = h+g+f+e+d+c+b+a
|
||||||
value = ((value >> 1) & 0x5555555555555555ULL) +
|
const uint64_t kMasks[] = {
|
||||||
(value & 0x5555555555555555ULL);
|
UINT64_C(0x5555555555555555),
|
||||||
value = ((value >> 2) & 0x3333333333333333ULL) +
|
UINT64_C(0x3333333333333333),
|
||||||
(value & 0x3333333333333333ULL);
|
UINT64_C(0x0f0f0f0f0f0f0f0f),
|
||||||
value = ((value >> 4) & 0x0f0f0f0f0f0f0f0fULL) +
|
UINT64_C(0x00ff00ff00ff00ff),
|
||||||
(value & 0x0f0f0f0f0f0f0f0fULL);
|
UINT64_C(0x0000ffff0000ffff),
|
||||||
value = ((value >> 8) & 0x00ff00ff00ff00ffULL) +
|
UINT64_C(0x00000000ffffffff),
|
||||||
(value & 0x00ff00ff00ff00ffULL);
|
};
|
||||||
value = ((value >> 16) & 0x0000ffff0000ffffULL) +
|
|
||||||
(value & 0x0000ffff0000ffffULL);
|
for (unsigned i = 0; i < (sizeof(kMasks) / sizeof(kMasks[0])); i++) {
|
||||||
value = ((value >> 32) & 0x00000000ffffffffULL) +
|
int shift = 1 << i;
|
||||||
(value & 0x00000000ffffffffULL);
|
value = ((value >> shift) & kMasks[i]) + (value & kMasks[i]);
|
||||||
|
}
|
||||||
|
|
||||||
return value;
|
return value;
|
||||||
}
|
}
|
||||||
|
|
|
@ -27,7 +27,7 @@
|
||||||
#ifndef VIXL_UTILS_H
|
#ifndef VIXL_UTILS_H
|
||||||
#define VIXL_UTILS_H
|
#define VIXL_UTILS_H
|
||||||
|
|
||||||
|
#include <math.h>
|
||||||
#include <string.h>
|
#include <string.h>
|
||||||
#include "globals.h"
|
#include "globals.h"
|
||||||
|
|
||||||
|
@ -35,19 +35,19 @@ namespace vixl {
|
||||||
|
|
||||||
// Check number width.
|
// Check number width.
|
||||||
inline bool is_intn(unsigned n, int64_t x) {
|
inline bool is_intn(unsigned n, int64_t x) {
|
||||||
ASSERT((0 < n) && (n < 64));
|
VIXL_ASSERT((0 < n) && (n < 64));
|
||||||
int64_t limit = 1ULL << (n - 1);
|
int64_t limit = INT64_C(1) << (n - 1);
|
||||||
return (-limit <= x) && (x < limit);
|
return (-limit <= x) && (x < limit);
|
||||||
}
|
}
|
||||||
|
|
||||||
inline bool is_uintn(unsigned n, int64_t x) {
|
inline bool is_uintn(unsigned n, int64_t x) {
|
||||||
ASSERT((0 < n) && (n < 64));
|
VIXL_ASSERT((0 < n) && (n < 64));
|
||||||
return !(x >> n);
|
return !(x >> n);
|
||||||
}
|
}
|
||||||
|
|
||||||
inline unsigned truncate_to_intn(unsigned n, int64_t x) {
|
inline unsigned truncate_to_intn(unsigned n, int64_t x) {
|
||||||
ASSERT((0 < n) && (n < 64));
|
VIXL_ASSERT((0 < n) && (n < 64));
|
||||||
return (x & ((1ULL << n) - 1));
|
return (x & ((INT64_C(1) << n) - 1));
|
||||||
}
|
}
|
||||||
|
|
||||||
#define INT_1_TO_63_LIST(V) \
|
#define INT_1_TO_63_LIST(V) \
|
||||||
|
@ -90,13 +90,67 @@ inline int64_t signed_bitextract_64(int msb, int lsb, int64_t x) {
|
||||||
return (x << (63 - msb)) >> (lsb + 63 - msb);
|
return (x << (63 - msb)) >> (lsb + 63 - msb);
|
||||||
}
|
}
|
||||||
|
|
||||||
// floating point representation
|
// Floating point representation.
|
||||||
uint32_t float_to_rawbits(float value);
|
uint32_t float_to_rawbits(float value);
|
||||||
uint64_t double_to_rawbits(double value);
|
uint64_t double_to_rawbits(double value);
|
||||||
float rawbits_to_float(uint32_t bits);
|
float rawbits_to_float(uint32_t bits);
|
||||||
double rawbits_to_double(uint64_t bits);
|
double rawbits_to_double(uint64_t bits);
|
||||||
|
|
||||||
// Bits counting.
|
|
||||||
|
// NaN tests.
|
||||||
|
inline bool IsSignallingNaN(double num) {
|
||||||
|
const uint64_t kFP64QuietNaNMask = UINT64_C(0x0008000000000000);
|
||||||
|
uint64_t raw = double_to_rawbits(num);
|
||||||
|
if (isnan(num) && ((raw & kFP64QuietNaNMask) == 0)) {
|
||||||
|
return true;
|
||||||
|
}
|
||||||
|
return false;
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
inline bool IsSignallingNaN(float num) {
|
||||||
|
const uint32_t kFP32QuietNaNMask = 0x00400000;
|
||||||
|
uint32_t raw = float_to_rawbits(num);
|
||||||
|
if (isnan(num) && ((raw & kFP32QuietNaNMask) == 0)) {
|
||||||
|
return true;
|
||||||
|
}
|
||||||
|
return false;
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
template <typename T>
|
||||||
|
inline bool IsQuietNaN(T num) {
|
||||||
|
return isnan(num) && !IsSignallingNaN(num);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
// Convert the NaN in 'num' to a quiet NaN.
|
||||||
|
inline double ToQuietNaN(double num) {
|
||||||
|
const uint64_t kFP64QuietNaNMask = UINT64_C(0x0008000000000000);
|
||||||
|
VIXL_ASSERT(isnan(num));
|
||||||
|
return rawbits_to_double(double_to_rawbits(num) | kFP64QuietNaNMask);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
inline float ToQuietNaN(float num) {
|
||||||
|
const uint32_t kFP32QuietNaNMask = 0x00400000;
|
||||||
|
VIXL_ASSERT(isnan(num));
|
||||||
|
return rawbits_to_float(float_to_rawbits(num) | kFP32QuietNaNMask);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
// Fused multiply-add.
|
||||||
|
inline double FusedMultiplyAdd(double op1, double op2, double a) {
|
||||||
|
return fma(op1, op2, a);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
inline float FusedMultiplyAdd(float op1, float op2, float a) {
|
||||||
|
return fmaf(op1, op2, a);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
// Bit counting.
|
||||||
int CountLeadingZeros(uint64_t value, int width);
|
int CountLeadingZeros(uint64_t value, int width);
|
||||||
int CountLeadingSignBits(int64_t value, int width);
|
int CountLeadingSignBits(int64_t value, int width);
|
||||||
int CountTrailingZeros(uint64_t value, int width);
|
int CountTrailingZeros(uint64_t value, int width);
|
||||||
|
@ -106,20 +160,30 @@ int CountSetBits(uint64_t value, int width);
|
||||||
// TODO: rename/refactor to make it specific to instructions.
|
// TODO: rename/refactor to make it specific to instructions.
|
||||||
template<typename T>
|
template<typename T>
|
||||||
bool IsWordAligned(T pointer) {
|
bool IsWordAligned(T pointer) {
|
||||||
ASSERT(sizeof(pointer) == sizeof(intptr_t)); // NOLINT(runtime/sizeof)
|
VIXL_ASSERT(sizeof(pointer) == sizeof(intptr_t)); // NOLINT(runtime/sizeof)
|
||||||
return (reinterpret_cast<intptr_t>(pointer) & 3) == 0;
|
return (reinterpret_cast<intptr_t>(pointer) & 3) == 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
// Increment a pointer until it has the specified alignment.
|
// Increment a pointer until it has the specified alignment.
|
||||||
template<class T>
|
template<class T>
|
||||||
T AlignUp(T pointer, size_t alignment) {
|
T AlignUp(T pointer, size_t alignment) {
|
||||||
ASSERT(sizeof(pointer) == sizeof(uintptr_t));
|
VIXL_STATIC_ASSERT(sizeof(pointer) == sizeof(uintptr_t));
|
||||||
uintptr_t pointer_raw = reinterpret_cast<uintptr_t>(pointer);
|
uintptr_t pointer_raw = reinterpret_cast<uintptr_t>(pointer);
|
||||||
size_t align_step = (alignment - pointer_raw) % alignment;
|
size_t align_step = (alignment - pointer_raw) % alignment;
|
||||||
ASSERT((pointer_raw + align_step) % alignment == 0);
|
VIXL_ASSERT((pointer_raw + align_step) % alignment == 0);
|
||||||
return reinterpret_cast<T>(pointer_raw + align_step);
|
return reinterpret_cast<T>(pointer_raw + align_step);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
// Decrement a pointer until it has the specified alignment.
|
||||||
|
template<class T>
|
||||||
|
T AlignDown(T pointer, size_t alignment) {
|
||||||
|
VIXL_STATIC_ASSERT(sizeof(pointer) == sizeof(uintptr_t));
|
||||||
|
uintptr_t pointer_raw = reinterpret_cast<uintptr_t>(pointer);
|
||||||
|
size_t align_step = pointer_raw % alignment;
|
||||||
|
VIXL_ASSERT((pointer_raw - align_step) % alignment == 0);
|
||||||
|
return reinterpret_cast<T>(pointer_raw - align_step);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
} // namespace vixl
|
} // namespace vixl
|
||||||
|
|
||||||
|
|
|
@ -134,7 +134,6 @@ static VMStateDescription vmstate_highbank_regs = {
|
||||||
.name = "highbank-regs",
|
.name = "highbank-regs",
|
||||||
.version_id = 0,
|
.version_id = 0,
|
||||||
.minimum_version_id = 0,
|
.minimum_version_id = 0,
|
||||||
.minimum_version_id_old = 0,
|
|
||||||
.fields = (VMStateField[]) {
|
.fields = (VMStateField[]) {
|
||||||
VMSTATE_UINT32_ARRAY(regs, HighbankRegsState, NUM_REGS),
|
VMSTATE_UINT32_ARRAY(regs, HighbankRegsState, NUM_REGS),
|
||||||
VMSTATE_END_OF_LIST(),
|
VMSTATE_END_OF_LIST(),
|
||||||
|
|
|
@ -405,7 +405,6 @@ static const VMStateDescription mv88w8618_eth_vmsd = {
|
||||||
.name = "mv88w8618_eth",
|
.name = "mv88w8618_eth",
|
||||||
.version_id = 1,
|
.version_id = 1,
|
||||||
.minimum_version_id = 1,
|
.minimum_version_id = 1,
|
||||||
.minimum_version_id_old = 1,
|
|
||||||
.fields = (VMStateField[]) {
|
.fields = (VMStateField[]) {
|
||||||
VMSTATE_UINT32(smir, mv88w8618_eth_state),
|
VMSTATE_UINT32(smir, mv88w8618_eth_state),
|
||||||
VMSTATE_UINT32(icr, mv88w8618_eth_state),
|
VMSTATE_UINT32(icr, mv88w8618_eth_state),
|
||||||
|
@ -642,7 +641,6 @@ static const VMStateDescription musicpal_lcd_vmsd = {
|
||||||
.name = "musicpal_lcd",
|
.name = "musicpal_lcd",
|
||||||
.version_id = 1,
|
.version_id = 1,
|
||||||
.minimum_version_id = 1,
|
.minimum_version_id = 1,
|
||||||
.minimum_version_id_old = 1,
|
|
||||||
.fields = (VMStateField[]) {
|
.fields = (VMStateField[]) {
|
||||||
VMSTATE_UINT32(brightness, musicpal_lcd_state),
|
VMSTATE_UINT32(brightness, musicpal_lcd_state),
|
||||||
VMSTATE_UINT32(mode, musicpal_lcd_state),
|
VMSTATE_UINT32(mode, musicpal_lcd_state),
|
||||||
|
@ -769,7 +767,6 @@ static const VMStateDescription mv88w8618_pic_vmsd = {
|
||||||
.name = "mv88w8618_pic",
|
.name = "mv88w8618_pic",
|
||||||
.version_id = 1,
|
.version_id = 1,
|
||||||
.minimum_version_id = 1,
|
.minimum_version_id = 1,
|
||||||
.minimum_version_id_old = 1,
|
|
||||||
.fields = (VMStateField[]) {
|
.fields = (VMStateField[]) {
|
||||||
VMSTATE_UINT32(level, mv88w8618_pic_state),
|
VMSTATE_UINT32(level, mv88w8618_pic_state),
|
||||||
VMSTATE_UINT32(enabled, mv88w8618_pic_state),
|
VMSTATE_UINT32(enabled, mv88w8618_pic_state),
|
||||||
|
@ -940,7 +937,6 @@ static const VMStateDescription mv88w8618_timer_vmsd = {
|
||||||
.name = "timer",
|
.name = "timer",
|
||||||
.version_id = 1,
|
.version_id = 1,
|
||||||
.minimum_version_id = 1,
|
.minimum_version_id = 1,
|
||||||
.minimum_version_id_old = 1,
|
|
||||||
.fields = (VMStateField[]) {
|
.fields = (VMStateField[]) {
|
||||||
VMSTATE_PTIMER(ptimer, mv88w8618_timer_state),
|
VMSTATE_PTIMER(ptimer, mv88w8618_timer_state),
|
||||||
VMSTATE_UINT32(limit, mv88w8618_timer_state),
|
VMSTATE_UINT32(limit, mv88w8618_timer_state),
|
||||||
|
@ -952,7 +948,6 @@ static const VMStateDescription mv88w8618_pit_vmsd = {
|
||||||
.name = "mv88w8618_pit",
|
.name = "mv88w8618_pit",
|
||||||
.version_id = 1,
|
.version_id = 1,
|
||||||
.minimum_version_id = 1,
|
.minimum_version_id = 1,
|
||||||
.minimum_version_id_old = 1,
|
|
||||||
.fields = (VMStateField[]) {
|
.fields = (VMStateField[]) {
|
||||||
VMSTATE_STRUCT_ARRAY(timer, mv88w8618_pit_state, 4, 1,
|
VMSTATE_STRUCT_ARRAY(timer, mv88w8618_pit_state, 4, 1,
|
||||||
mv88w8618_timer_vmsd, mv88w8618_timer_state),
|
mv88w8618_timer_vmsd, mv88w8618_timer_state),
|
||||||
|
@ -1041,7 +1036,6 @@ static const VMStateDescription mv88w8618_flashcfg_vmsd = {
|
||||||
.name = "mv88w8618_flashcfg",
|
.name = "mv88w8618_flashcfg",
|
||||||
.version_id = 1,
|
.version_id = 1,
|
||||||
.minimum_version_id = 1,
|
.minimum_version_id = 1,
|
||||||
.minimum_version_id_old = 1,
|
|
||||||
.fields = (VMStateField[]) {
|
.fields = (VMStateField[]) {
|
||||||
VMSTATE_UINT32(cfgr0, mv88w8618_flashcfg_state),
|
VMSTATE_UINT32(cfgr0, mv88w8618_flashcfg_state),
|
||||||
VMSTATE_END_OF_LIST()
|
VMSTATE_END_OF_LIST()
|
||||||
|
@ -1381,7 +1375,6 @@ static const VMStateDescription musicpal_gpio_vmsd = {
|
||||||
.name = "musicpal_gpio",
|
.name = "musicpal_gpio",
|
||||||
.version_id = 1,
|
.version_id = 1,
|
||||||
.minimum_version_id = 1,
|
.minimum_version_id = 1,
|
||||||
.minimum_version_id_old = 1,
|
|
||||||
.fields = (VMStateField[]) {
|
.fields = (VMStateField[]) {
|
||||||
VMSTATE_UINT32(lcd_brightness, musicpal_gpio_state),
|
VMSTATE_UINT32(lcd_brightness, musicpal_gpio_state),
|
||||||
VMSTATE_UINT32(out_state, musicpal_gpio_state),
|
VMSTATE_UINT32(out_state, musicpal_gpio_state),
|
||||||
|
@ -1548,7 +1541,6 @@ static const VMStateDescription musicpal_key_vmsd = {
|
||||||
.name = "musicpal_key",
|
.name = "musicpal_key",
|
||||||
.version_id = 1,
|
.version_id = 1,
|
||||||
.minimum_version_id = 1,
|
.minimum_version_id = 1,
|
||||||
.minimum_version_id_old = 1,
|
|
||||||
.fields = (VMStateField[]) {
|
.fields = (VMStateField[]) {
|
||||||
VMSTATE_UINT32(kbd_extended, musicpal_key_state),
|
VMSTATE_UINT32(kbd_extended, musicpal_key_state),
|
||||||
VMSTATE_UINT32(pressed_keys, musicpal_key_state),
|
VMSTATE_UINT32(pressed_keys, musicpal_key_state),
|
||||||
|
|
|
@ -2709,8 +2709,8 @@ static void omap_rtc_write(void *opaque, hwaddr addr,
|
||||||
s->ti += ti[1];
|
s->ti += ti[1];
|
||||||
} else {
|
} else {
|
||||||
/* A less accurate version */
|
/* A less accurate version */
|
||||||
s->ti -= (s->current_tm.tm_year % 100) * 31536000;
|
s->ti -= (time_t)(s->current_tm.tm_year % 100) * 31536000;
|
||||||
s->ti += from_bcd(value) * 31536000;
|
s->ti += (time_t)from_bcd(value) * 31536000;
|
||||||
}
|
}
|
||||||
return;
|
return;
|
||||||
|
|
||||||
|
|
|
@ -148,7 +148,6 @@ static const VMStateDescription vmstate_pxa2xx_pm = {
|
||||||
.name = "pxa2xx_pm",
|
.name = "pxa2xx_pm",
|
||||||
.version_id = 0,
|
.version_id = 0,
|
||||||
.minimum_version_id = 0,
|
.minimum_version_id = 0,
|
||||||
.minimum_version_id_old = 0,
|
|
||||||
.fields = (VMStateField[]) {
|
.fields = (VMStateField[]) {
|
||||||
VMSTATE_UINT32_ARRAY(pm_regs, PXA2xxState, 0x40),
|
VMSTATE_UINT32_ARRAY(pm_regs, PXA2xxState, 0x40),
|
||||||
VMSTATE_END_OF_LIST()
|
VMSTATE_END_OF_LIST()
|
||||||
|
@ -215,7 +214,6 @@ static const VMStateDescription vmstate_pxa2xx_cm = {
|
||||||
.name = "pxa2xx_cm",
|
.name = "pxa2xx_cm",
|
||||||
.version_id = 0,
|
.version_id = 0,
|
||||||
.minimum_version_id = 0,
|
.minimum_version_id = 0,
|
||||||
.minimum_version_id_old = 0,
|
|
||||||
.fields = (VMStateField[]) {
|
.fields = (VMStateField[]) {
|
||||||
VMSTATE_UINT32_ARRAY(cm_regs, PXA2xxState, 4),
|
VMSTATE_UINT32_ARRAY(cm_regs, PXA2xxState, 4),
|
||||||
VMSTATE_UINT32(clkcfg, PXA2xxState),
|
VMSTATE_UINT32(clkcfg, PXA2xxState),
|
||||||
|
@ -440,7 +438,6 @@ static const VMStateDescription vmstate_pxa2xx_mm = {
|
||||||
.name = "pxa2xx_mm",
|
.name = "pxa2xx_mm",
|
||||||
.version_id = 0,
|
.version_id = 0,
|
||||||
.minimum_version_id = 0,
|
.minimum_version_id = 0,
|
||||||
.minimum_version_id_old = 0,
|
|
||||||
.fields = (VMStateField[]) {
|
.fields = (VMStateField[]) {
|
||||||
VMSTATE_UINT32_ARRAY(mm_regs, PXA2xxState, 0x1a),
|
VMSTATE_UINT32_ARRAY(mm_regs, PXA2xxState, 0x1a),
|
||||||
VMSTATE_END_OF_LIST()
|
VMSTATE_END_OF_LIST()
|
||||||
|
@ -1172,7 +1169,6 @@ static const VMStateDescription vmstate_pxa2xx_rtc_regs = {
|
||||||
.name = "pxa2xx_rtc",
|
.name = "pxa2xx_rtc",
|
||||||
.version_id = 0,
|
.version_id = 0,
|
||||||
.minimum_version_id = 0,
|
.minimum_version_id = 0,
|
||||||
.minimum_version_id_old = 0,
|
|
||||||
.pre_save = pxa2xx_rtc_pre_save,
|
.pre_save = pxa2xx_rtc_pre_save,
|
||||||
.post_load = pxa2xx_rtc_post_load,
|
.post_load = pxa2xx_rtc_post_load,
|
||||||
.fields = (VMStateField[]) {
|
.fields = (VMStateField[]) {
|
||||||
|
@ -1436,8 +1432,7 @@ static const VMStateDescription vmstate_pxa2xx_i2c_slave = {
|
||||||
.name = "pxa2xx_i2c_slave",
|
.name = "pxa2xx_i2c_slave",
|
||||||
.version_id = 1,
|
.version_id = 1,
|
||||||
.minimum_version_id = 1,
|
.minimum_version_id = 1,
|
||||||
.minimum_version_id_old = 1,
|
.fields = (VMStateField[]) {
|
||||||
.fields = (VMStateField []) {
|
|
||||||
VMSTATE_I2C_SLAVE(parent_obj, PXA2xxI2CSlaveState),
|
VMSTATE_I2C_SLAVE(parent_obj, PXA2xxI2CSlaveState),
|
||||||
VMSTATE_END_OF_LIST()
|
VMSTATE_END_OF_LIST()
|
||||||
}
|
}
|
||||||
|
@ -1447,8 +1442,7 @@ static const VMStateDescription vmstate_pxa2xx_i2c = {
|
||||||
.name = "pxa2xx_i2c",
|
.name = "pxa2xx_i2c",
|
||||||
.version_id = 1,
|
.version_id = 1,
|
||||||
.minimum_version_id = 1,
|
.minimum_version_id = 1,
|
||||||
.minimum_version_id_old = 1,
|
.fields = (VMStateField[]) {
|
||||||
.fields = (VMStateField []) {
|
|
||||||
VMSTATE_UINT16(control, PXA2xxI2CState),
|
VMSTATE_UINT16(control, PXA2xxI2CState),
|
||||||
VMSTATE_UINT16(status, PXA2xxI2CState),
|
VMSTATE_UINT16(status, PXA2xxI2CState),
|
||||||
VMSTATE_UINT8(ibmr, PXA2xxI2CState),
|
VMSTATE_UINT8(ibmr, PXA2xxI2CState),
|
||||||
|
@ -1705,7 +1699,6 @@ static const VMStateDescription vmstate_pxa2xx_i2s = {
|
||||||
.name = "pxa2xx_i2s",
|
.name = "pxa2xx_i2s",
|
||||||
.version_id = 0,
|
.version_id = 0,
|
||||||
.minimum_version_id = 0,
|
.minimum_version_id = 0,
|
||||||
.minimum_version_id_old = 0,
|
|
||||||
.fields = (VMStateField[]) {
|
.fields = (VMStateField[]) {
|
||||||
VMSTATE_UINT32_ARRAY(control, PXA2xxI2SState, 2),
|
VMSTATE_UINT32_ARRAY(control, PXA2xxI2SState, 2),
|
||||||
VMSTATE_UINT32(status, PXA2xxI2SState),
|
VMSTATE_UINT32(status, PXA2xxI2SState),
|
||||||
|
|
|
@ -313,8 +313,7 @@ static const VMStateDescription vmstate_pxa2xx_gpio_regs = {
|
||||||
.name = "pxa2xx-gpio",
|
.name = "pxa2xx-gpio",
|
||||||
.version_id = 1,
|
.version_id = 1,
|
||||||
.minimum_version_id = 1,
|
.minimum_version_id = 1,
|
||||||
.minimum_version_id_old = 1,
|
.fields = (VMStateField[]) {
|
||||||
.fields = (VMStateField []) {
|
|
||||||
VMSTATE_INT32(lines, PXA2xxGPIOInfo),
|
VMSTATE_INT32(lines, PXA2xxGPIOInfo),
|
||||||
VMSTATE_UINT32_ARRAY(ilevel, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS),
|
VMSTATE_UINT32_ARRAY(ilevel, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS),
|
||||||
VMSTATE_UINT32_ARRAY(olevel, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS),
|
VMSTATE_UINT32_ARRAY(olevel, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS),
|
||||||
|
|
|
@ -296,7 +296,6 @@ static VMStateDescription vmstate_pxa2xx_pic_regs = {
|
||||||
.name = "pxa2xx_pic",
|
.name = "pxa2xx_pic",
|
||||||
.version_id = 0,
|
.version_id = 0,
|
||||||
.minimum_version_id = 0,
|
.minimum_version_id = 0,
|
||||||
.minimum_version_id_old = 0,
|
|
||||||
.post_load = pxa2xx_pic_post_load,
|
.post_load = pxa2xx_pic_post_load,
|
||||||
.fields = (VMStateField[]) {
|
.fields = (VMStateField[]) {
|
||||||
VMSTATE_UINT32_ARRAY(int_enabled, PXA2xxPICState, 2),
|
VMSTATE_UINT32_ARRAY(int_enabled, PXA2xxPICState, 2),
|
||||||
|
|
|
@ -1006,8 +1006,7 @@ static VMStateDescription vmstate_sl_nand_info = {
|
||||||
.name = "sl-nand",
|
.name = "sl-nand",
|
||||||
.version_id = 0,
|
.version_id = 0,
|
||||||
.minimum_version_id = 0,
|
.minimum_version_id = 0,
|
||||||
.minimum_version_id_old = 0,
|
.fields = (VMStateField[]) {
|
||||||
.fields = (VMStateField []) {
|
|
||||||
VMSTATE_UINT8(ctl, SLNANDState),
|
VMSTATE_UINT8(ctl, SLNANDState),
|
||||||
VMSTATE_STRUCT(ecc, SLNANDState, 0, vmstate_ecc_state, ECCState),
|
VMSTATE_STRUCT(ecc, SLNANDState, 0, vmstate_ecc_state, ECCState),
|
||||||
VMSTATE_END_OF_LIST(),
|
VMSTATE_END_OF_LIST(),
|
||||||
|
@ -1041,9 +1040,8 @@ static VMStateDescription vmstate_spitz_kbd = {
|
||||||
.name = "spitz-keyboard",
|
.name = "spitz-keyboard",
|
||||||
.version_id = 1,
|
.version_id = 1,
|
||||||
.minimum_version_id = 0,
|
.minimum_version_id = 0,
|
||||||
.minimum_version_id_old = 0,
|
|
||||||
.post_load = spitz_keyboard_post_load,
|
.post_load = spitz_keyboard_post_load,
|
||||||
.fields = (VMStateField []) {
|
.fields = (VMStateField[]) {
|
||||||
VMSTATE_UINT16(sense_state, SpitzKeyboardState),
|
VMSTATE_UINT16(sense_state, SpitzKeyboardState),
|
||||||
VMSTATE_UINT16(strobe_state, SpitzKeyboardState),
|
VMSTATE_UINT16(strobe_state, SpitzKeyboardState),
|
||||||
VMSTATE_UNUSED_TEST(is_version_0, 5),
|
VMSTATE_UNUSED_TEST(is_version_0, 5),
|
||||||
|
@ -1076,8 +1074,7 @@ static const VMStateDescription vmstate_corgi_ssp_regs = {
|
||||||
.name = "corgi-ssp",
|
.name = "corgi-ssp",
|
||||||
.version_id = 2,
|
.version_id = 2,
|
||||||
.minimum_version_id = 2,
|
.minimum_version_id = 2,
|
||||||
.minimum_version_id_old = 2,
|
.fields = (VMStateField[]) {
|
||||||
.fields = (VMStateField []) {
|
|
||||||
VMSTATE_SSI_SLAVE(ssidev, CorgiSSPState),
|
VMSTATE_SSI_SLAVE(ssidev, CorgiSSPState),
|
||||||
VMSTATE_UINT32_ARRAY(enable, CorgiSSPState, 3),
|
VMSTATE_UINT32_ARRAY(enable, CorgiSSPState, 3),
|
||||||
VMSTATE_END_OF_LIST(),
|
VMSTATE_END_OF_LIST(),
|
||||||
|
@ -1105,8 +1102,7 @@ static const VMStateDescription vmstate_spitz_lcdtg_regs = {
|
||||||
.name = "spitz-lcdtg",
|
.name = "spitz-lcdtg",
|
||||||
.version_id = 1,
|
.version_id = 1,
|
||||||
.minimum_version_id = 1,
|
.minimum_version_id = 1,
|
||||||
.minimum_version_id_old = 1,
|
.fields = (VMStateField[]) {
|
||||||
.fields = (VMStateField []) {
|
|
||||||
VMSTATE_SSI_SLAVE(ssidev, SpitzLCDTG),
|
VMSTATE_SSI_SLAVE(ssidev, SpitzLCDTG),
|
||||||
VMSTATE_UINT32(bl_intensity, SpitzLCDTG),
|
VMSTATE_UINT32(bl_intensity, SpitzLCDTG),
|
||||||
VMSTATE_UINT32(bl_power, SpitzLCDTG),
|
VMSTATE_UINT32(bl_power, SpitzLCDTG),
|
||||||
|
|
|
@ -185,12 +185,19 @@ static uint64_t gptm_read(void *opaque, hwaddr offset,
|
||||||
case 0x44: /* TBPMR */
|
case 0x44: /* TBPMR */
|
||||||
return s->match_prescale[1];
|
return s->match_prescale[1];
|
||||||
case 0x48: /* TAR */
|
case 0x48: /* TAR */
|
||||||
if (s->control == 1)
|
if (s->config == 1) {
|
||||||
return s->rtc;
|
return s->rtc;
|
||||||
|
}
|
||||||
|
qemu_log_mask(LOG_UNIMP,
|
||||||
|
"GPTM: read of TAR but timer read not supported");
|
||||||
|
return 0;
|
||||||
case 0x4c: /* TBR */
|
case 0x4c: /* TBR */
|
||||||
hw_error("TODO: Timer value read\n");
|
qemu_log_mask(LOG_UNIMP,
|
||||||
|
"GPTM: read of TBR but timer read not supported");
|
||||||
|
return 0;
|
||||||
default:
|
default:
|
||||||
hw_error("gptm_read: Bad offset 0x%x\n", (int)offset);
|
qemu_log_mask(LOG_GUEST_ERROR,
|
||||||
|
"GPTM: read at bad offset 0x%x\n", (int)offset);
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
@ -286,7 +293,6 @@ static const VMStateDescription vmstate_stellaris_gptm = {
|
||||||
.name = "stellaris_gptm",
|
.name = "stellaris_gptm",
|
||||||
.version_id = 1,
|
.version_id = 1,
|
||||||
.minimum_version_id = 1,
|
.minimum_version_id = 1,
|
||||||
.minimum_version_id_old = 1,
|
|
||||||
.fields = (VMStateField[]) {
|
.fields = (VMStateField[]) {
|
||||||
VMSTATE_UINT32(config, gptm_state),
|
VMSTATE_UINT32(config, gptm_state),
|
||||||
VMSTATE_UINT32_ARRAY(mode, gptm_state, 2),
|
VMSTATE_UINT32_ARRAY(mode, gptm_state, 2),
|
||||||
|
@ -643,7 +649,6 @@ static const VMStateDescription vmstate_stellaris_sys = {
|
||||||
.name = "stellaris_sys",
|
.name = "stellaris_sys",
|
||||||
.version_id = 2,
|
.version_id = 2,
|
||||||
.minimum_version_id = 1,
|
.minimum_version_id = 1,
|
||||||
.minimum_version_id_old = 1,
|
|
||||||
.post_load = stellaris_sys_post_load,
|
.post_load = stellaris_sys_post_load,
|
||||||
.fields = (VMStateField[]) {
|
.fields = (VMStateField[]) {
|
||||||
VMSTATE_UINT32(pborctl, ssys_state),
|
VMSTATE_UINT32(pborctl, ssys_state),
|
||||||
|
@ -851,7 +856,6 @@ static const VMStateDescription vmstate_stellaris_i2c = {
|
||||||
.name = "stellaris_i2c",
|
.name = "stellaris_i2c",
|
||||||
.version_id = 1,
|
.version_id = 1,
|
||||||
.minimum_version_id = 1,
|
.minimum_version_id = 1,
|
||||||
.minimum_version_id_old = 1,
|
|
||||||
.fields = (VMStateField[]) {
|
.fields = (VMStateField[]) {
|
||||||
VMSTATE_UINT32(msa, stellaris_i2c_state),
|
VMSTATE_UINT32(msa, stellaris_i2c_state),
|
||||||
VMSTATE_UINT32(mcs, stellaris_i2c_state),
|
VMSTATE_UINT32(mcs, stellaris_i2c_state),
|
||||||
|
@ -1121,7 +1125,6 @@ static const VMStateDescription vmstate_stellaris_adc = {
|
||||||
.name = "stellaris_adc",
|
.name = "stellaris_adc",
|
||||||
.version_id = 1,
|
.version_id = 1,
|
||||||
.minimum_version_id = 1,
|
.minimum_version_id = 1,
|
||||||
.minimum_version_id_old = 1,
|
|
||||||
.fields = (VMStateField[]) {
|
.fields = (VMStateField[]) {
|
||||||
VMSTATE_UINT32(actss, stellaris_adc_state),
|
VMSTATE_UINT32(actss, stellaris_adc_state),
|
||||||
VMSTATE_UINT32(ris, stellaris_adc_state),
|
VMSTATE_UINT32(ris, stellaris_adc_state),
|
||||||
|
|
|
@ -199,7 +199,6 @@ static VMStateDescription vmstate_strongarm_pic_regs = {
|
||||||
.name = "strongarm_pic",
|
.name = "strongarm_pic",
|
||||||
.version_id = 0,
|
.version_id = 0,
|
||||||
.minimum_version_id = 0,
|
.minimum_version_id = 0,
|
||||||
.minimum_version_id_old = 0,
|
|
||||||
.post_load = strongarm_pic_post_load,
|
.post_load = strongarm_pic_post_load,
|
||||||
.fields = (VMStateField[]) {
|
.fields = (VMStateField[]) {
|
||||||
VMSTATE_UINT32(pending, StrongARMPICState),
|
VMSTATE_UINT32(pending, StrongARMPICState),
|
||||||
|
@ -424,7 +423,6 @@ static const VMStateDescription vmstate_strongarm_rtc_regs = {
|
||||||
.name = "strongarm-rtc",
|
.name = "strongarm-rtc",
|
||||||
.version_id = 0,
|
.version_id = 0,
|
||||||
.minimum_version_id = 0,
|
.minimum_version_id = 0,
|
||||||
.minimum_version_id_old = 0,
|
|
||||||
.pre_save = strongarm_rtc_pre_save,
|
.pre_save = strongarm_rtc_pre_save,
|
||||||
.post_load = strongarm_rtc_post_load,
|
.post_load = strongarm_rtc_post_load,
|
||||||
.fields = (VMStateField[]) {
|
.fields = (VMStateField[]) {
|
||||||
|
@ -670,7 +668,6 @@ static const VMStateDescription vmstate_strongarm_gpio_regs = {
|
||||||
.name = "strongarm-gpio",
|
.name = "strongarm-gpio",
|
||||||
.version_id = 0,
|
.version_id = 0,
|
||||||
.minimum_version_id = 0,
|
.minimum_version_id = 0,
|
||||||
.minimum_version_id_old = 0,
|
|
||||||
.fields = (VMStateField[]) {
|
.fields = (VMStateField[]) {
|
||||||
VMSTATE_UINT32(ilevel, StrongARMGPIOInfo),
|
VMSTATE_UINT32(ilevel, StrongARMGPIOInfo),
|
||||||
VMSTATE_UINT32(olevel, StrongARMGPIOInfo),
|
VMSTATE_UINT32(olevel, StrongARMGPIOInfo),
|
||||||
|
@ -842,7 +839,6 @@ static const VMStateDescription vmstate_strongarm_ppc_regs = {
|
||||||
.name = "strongarm-ppc",
|
.name = "strongarm-ppc",
|
||||||
.version_id = 0,
|
.version_id = 0,
|
||||||
.minimum_version_id = 0,
|
.minimum_version_id = 0,
|
||||||
.minimum_version_id_old = 0,
|
|
||||||
.fields = (VMStateField[]) {
|
.fields = (VMStateField[]) {
|
||||||
VMSTATE_UINT32(ilevel, StrongARMPPCInfo),
|
VMSTATE_UINT32(ilevel, StrongARMPPCInfo),
|
||||||
VMSTATE_UINT32(olevel, StrongARMPPCInfo),
|
VMSTATE_UINT32(olevel, StrongARMPPCInfo),
|
||||||
|
@ -1293,7 +1289,6 @@ static const VMStateDescription vmstate_strongarm_uart_regs = {
|
||||||
.name = "strongarm-uart",
|
.name = "strongarm-uart",
|
||||||
.version_id = 0,
|
.version_id = 0,
|
||||||
.minimum_version_id = 0,
|
.minimum_version_id = 0,
|
||||||
.minimum_version_id_old = 0,
|
|
||||||
.post_load = strongarm_uart_post_load,
|
.post_load = strongarm_uart_post_load,
|
||||||
.fields = (VMStateField[]) {
|
.fields = (VMStateField[]) {
|
||||||
VMSTATE_UINT8(utcr0, StrongARMUARTState),
|
VMSTATE_UINT8(utcr0, StrongARMUARTState),
|
||||||
|
@ -1553,7 +1548,6 @@ static const VMStateDescription vmstate_strongarm_ssp_regs = {
|
||||||
.name = "strongarm-ssp",
|
.name = "strongarm-ssp",
|
||||||
.version_id = 0,
|
.version_id = 0,
|
||||||
.minimum_version_id = 0,
|
.minimum_version_id = 0,
|
||||||
.minimum_version_id_old = 0,
|
|
||||||
.post_load = strongarm_ssp_post_load,
|
.post_load = strongarm_ssp_post_load,
|
||||||
.fields = (VMStateField[]) {
|
.fields = (VMStateField[]) {
|
||||||
VMSTATE_UINT16_ARRAY(sscr, StrongARMSSPState, 2),
|
VMSTATE_UINT16_ARRAY(sscr, StrongARMSSPState, 2),
|
||||||
|
|
|
@ -164,7 +164,6 @@ static VMStateDescription vmstate_zipit_lcd_state = {
|
||||||
.name = "zipit-lcd",
|
.name = "zipit-lcd",
|
||||||
.version_id = 2,
|
.version_id = 2,
|
||||||
.minimum_version_id = 2,
|
.minimum_version_id = 2,
|
||||||
.minimum_version_id_old = 2,
|
|
||||||
.fields = (VMStateField[]) {
|
.fields = (VMStateField[]) {
|
||||||
VMSTATE_SSI_SLAVE(ssidev, ZipitLCD),
|
VMSTATE_SSI_SLAVE(ssidev, ZipitLCD),
|
||||||
VMSTATE_INT32(selected, ZipitLCD),
|
VMSTATE_INT32(selected, ZipitLCD),
|
||||||
|
@ -275,7 +274,6 @@ static VMStateDescription vmstate_aer915_state = {
|
||||||
.name = "aer915",
|
.name = "aer915",
|
||||||
.version_id = 1,
|
.version_id = 1,
|
||||||
.minimum_version_id = 1,
|
.minimum_version_id = 1,
|
||||||
.minimum_version_id_old = 1,
|
|
||||||
.fields = (VMStateField[]) {
|
.fields = (VMStateField[]) {
|
||||||
VMSTATE_INT32(len, AER915State),
|
VMSTATE_INT32(len, AER915State),
|
||||||
VMSTATE_BUFFER(buf, AER915State),
|
VMSTATE_BUFFER(buf, AER915State),
|
||||||
|
|
|
@ -324,8 +324,7 @@ const VMStateDescription vmstate_lm4549_state = {
|
||||||
.name = "lm4549_state",
|
.name = "lm4549_state",
|
||||||
.version_id = 1,
|
.version_id = 1,
|
||||||
.minimum_version_id = 1,
|
.minimum_version_id = 1,
|
||||||
.minimum_version_id_old = 1,
|
.post_load = lm4549_post_load,
|
||||||
.post_load = &lm4549_post_load,
|
|
||||||
.fields = (VMStateField[]) {
|
.fields = (VMStateField[]) {
|
||||||
VMSTATE_UINT32(voice_is_active, lm4549_state),
|
VMSTATE_UINT32(voice_is_active, lm4549_state),
|
||||||
VMSTATE_UINT16_ARRAY(regfile, lm4549_state, 128),
|
VMSTATE_UINT16_ARRAY(regfile, lm4549_state, 128),
|
||||||
|
|
|
@ -259,7 +259,6 @@ static const VMStateDescription mv88w8618_audio_vmsd = {
|
||||||
.name = "mv88w8618_audio",
|
.name = "mv88w8618_audio",
|
||||||
.version_id = 1,
|
.version_id = 1,
|
||||||
.minimum_version_id = 1,
|
.minimum_version_id = 1,
|
||||||
.minimum_version_id_old = 1,
|
|
||||||
.fields = (VMStateField[]) {
|
.fields = (VMStateField[]) {
|
||||||
VMSTATE_UINT32(playback_mode, mv88w8618_audio_state),
|
VMSTATE_UINT32(playback_mode, mv88w8618_audio_state),
|
||||||
VMSTATE_UINT32(status, mv88w8618_audio_state),
|
VMSTATE_UINT32(status, mv88w8618_audio_state),
|
||||||
|
|
|
@ -561,7 +561,6 @@ static const VMStateDescription vmstate_pl041_regfile = {
|
||||||
.name = "pl041_regfile",
|
.name = "pl041_regfile",
|
||||||
.version_id = 1,
|
.version_id = 1,
|
||||||
.minimum_version_id = 1,
|
.minimum_version_id = 1,
|
||||||
.minimum_version_id_old = 1,
|
|
||||||
.fields = (VMStateField[]) {
|
.fields = (VMStateField[]) {
|
||||||
#define REGISTER(name, offset) VMSTATE_UINT32(name, pl041_regfile),
|
#define REGISTER(name, offset) VMSTATE_UINT32(name, pl041_regfile),
|
||||||
#include "pl041.hx"
|
#include "pl041.hx"
|
||||||
|
@ -574,7 +573,6 @@ static const VMStateDescription vmstate_pl041_fifo = {
|
||||||
.name = "pl041_fifo",
|
.name = "pl041_fifo",
|
||||||
.version_id = 1,
|
.version_id = 1,
|
||||||
.minimum_version_id = 1,
|
.minimum_version_id = 1,
|
||||||
.minimum_version_id_old = 1,
|
|
||||||
.fields = (VMStateField[]) {
|
.fields = (VMStateField[]) {
|
||||||
VMSTATE_UINT32(level, pl041_fifo),
|
VMSTATE_UINT32(level, pl041_fifo),
|
||||||
VMSTATE_UINT32_ARRAY(data, pl041_fifo, MAX_FIFO_DEPTH),
|
VMSTATE_UINT32_ARRAY(data, pl041_fifo, MAX_FIFO_DEPTH),
|
||||||
|
@ -586,7 +584,6 @@ static const VMStateDescription vmstate_pl041_channel = {
|
||||||
.name = "pl041_channel",
|
.name = "pl041_channel",
|
||||||
.version_id = 1,
|
.version_id = 1,
|
||||||
.minimum_version_id = 1,
|
.minimum_version_id = 1,
|
||||||
.minimum_version_id_old = 1,
|
|
||||||
.fields = (VMStateField[]) {
|
.fields = (VMStateField[]) {
|
||||||
VMSTATE_STRUCT(tx_fifo, pl041_channel, 0,
|
VMSTATE_STRUCT(tx_fifo, pl041_channel, 0,
|
||||||
vmstate_pl041_fifo, pl041_fifo),
|
vmstate_pl041_fifo, pl041_fifo),
|
||||||
|
|
|
@ -583,10 +583,9 @@ static const VMStateDescription vmstate_wm8750 = {
|
||||||
.name = CODEC,
|
.name = CODEC,
|
||||||
.version_id = 0,
|
.version_id = 0,
|
||||||
.minimum_version_id = 0,
|
.minimum_version_id = 0,
|
||||||
.minimum_version_id_old = 0,
|
|
||||||
.pre_save = wm8750_pre_save,
|
.pre_save = wm8750_pre_save,
|
||||||
.post_load = wm8750_post_load,
|
.post_load = wm8750_post_load,
|
||||||
.fields = (VMStateField []) {
|
.fields = (VMStateField[]) {
|
||||||
VMSTATE_UINT8_ARRAY(i2c_data, WM8750State, 2),
|
VMSTATE_UINT8_ARRAY(i2c_data, WM8750State, 2),
|
||||||
VMSTATE_INT32(i2c_len, WM8750State),
|
VMSTATE_INT32(i2c_len, WM8750State),
|
||||||
VMSTATE_INT32(enable, WM8750State),
|
VMSTATE_INT32(enable, WM8750State),
|
||||||
|
|
|
@ -81,8 +81,7 @@ VMStateDescription vmstate_ecc_state = {
|
||||||
.name = "ecc-state",
|
.name = "ecc-state",
|
||||||
.version_id = 0,
|
.version_id = 0,
|
||||||
.minimum_version_id = 0,
|
.minimum_version_id = 0,
|
||||||
.minimum_version_id_old = 0,
|
.fields = (VMStateField[]) {
|
||||||
.fields = (VMStateField []) {
|
|
||||||
VMSTATE_UINT8(cp, ECCState),
|
VMSTATE_UINT8(cp, ECCState),
|
||||||
VMSTATE_UINT16_ARRAY(lp, ECCState, 2),
|
VMSTATE_UINT16_ARRAY(lp, ECCState, 2),
|
||||||
VMSTATE_UINT16(count, ECCState),
|
VMSTATE_UINT16(count, ECCState),
|
||||||
|
|
|
@ -346,7 +346,6 @@ static const VMStateDescription vmstate_nand = {
|
||||||
.name = "nand",
|
.name = "nand",
|
||||||
.version_id = 1,
|
.version_id = 1,
|
||||||
.minimum_version_id = 1,
|
.minimum_version_id = 1,
|
||||||
.minimum_version_id_old = 1,
|
|
||||||
.pre_save = nand_pre_save,
|
.pre_save = nand_pre_save,
|
||||||
.post_load = nand_post_load,
|
.post_load = nand_post_load,
|
||||||
.fields = (VMStateField[]) {
|
.fields = (VMStateField[]) {
|
||||||
|
|
|
@ -169,7 +169,6 @@ static const VMStateDescription vmstate_onenand = {
|
||||||
.name = "onenand",
|
.name = "onenand",
|
||||||
.version_id = 1,
|
.version_id = 1,
|
||||||
.minimum_version_id = 1,
|
.minimum_version_id = 1,
|
||||||
.minimum_version_id_old = 1,
|
|
||||||
.pre_save = onenand_pre_save,
|
.pre_save = onenand_pre_save,
|
||||||
.post_load = onenand_post_load,
|
.post_load = onenand_post_load,
|
||||||
.fields = (VMStateField[]) {
|
.fields = (VMStateField[]) {
|
||||||
|
|
|
@ -504,7 +504,6 @@ static const VMStateDescription vmstate_cadence_uart = {
|
||||||
.name = "cadence_uart",
|
.name = "cadence_uart",
|
||||||
.version_id = 2,
|
.version_id = 2,
|
||||||
.minimum_version_id = 2,
|
.minimum_version_id = 2,
|
||||||
.minimum_version_id_old = 2,
|
|
||||||
.post_load = cadence_uart_post_load,
|
.post_load = cadence_uart_post_load,
|
||||||
.fields = (VMStateField[]) {
|
.fields = (VMStateField[]) {
|
||||||
VMSTATE_UINT32_ARRAY(r, UartState, R_MAX),
|
VMSTATE_UINT32_ARRAY(r, UartState, R_MAX),
|
||||||
|
|
|
@ -162,7 +162,6 @@ static const VMStateDescription vmstate_digic_uart = {
|
||||||
.name = "digic-uart",
|
.name = "digic-uart",
|
||||||
.version_id = 1,
|
.version_id = 1,
|
||||||
.minimum_version_id = 1,
|
.minimum_version_id = 1,
|
||||||
.minimum_version_id_old = 1,
|
|
||||||
.fields = (VMStateField[]) {
|
.fields = (VMStateField[]) {
|
||||||
VMSTATE_UINT32(reg_rx, DigicUartState),
|
VMSTATE_UINT32(reg_rx, DigicUartState),
|
||||||
VMSTATE_UINT32(reg_st, DigicUartState),
|
VMSTATE_UINT32(reg_st, DigicUartState),
|
||||||
|
|
|
@ -560,7 +560,6 @@ static const VMStateDescription vmstate_exynos4210_uart_fifo = {
|
||||||
.name = "exynos4210.uart.fifo",
|
.name = "exynos4210.uart.fifo",
|
||||||
.version_id = 1,
|
.version_id = 1,
|
||||||
.minimum_version_id = 1,
|
.minimum_version_id = 1,
|
||||||
.minimum_version_id_old = 1,
|
|
||||||
.fields = (VMStateField[]) {
|
.fields = (VMStateField[]) {
|
||||||
VMSTATE_UINT32(sp, Exynos4210UartFIFO),
|
VMSTATE_UINT32(sp, Exynos4210UartFIFO),
|
||||||
VMSTATE_UINT32(rp, Exynos4210UartFIFO),
|
VMSTATE_UINT32(rp, Exynos4210UartFIFO),
|
||||||
|
@ -573,7 +572,6 @@ static const VMStateDescription vmstate_exynos4210_uart = {
|
||||||
.name = "exynos4210.uart",
|
.name = "exynos4210.uart",
|
||||||
.version_id = 1,
|
.version_id = 1,
|
||||||
.minimum_version_id = 1,
|
.minimum_version_id = 1,
|
||||||
.minimum_version_id_old = 1,
|
|
||||||
.fields = (VMStateField[]) {
|
.fields = (VMStateField[]) {
|
||||||
VMSTATE_STRUCT(rx, Exynos4210UartState, 1,
|
VMSTATE_STRUCT(rx, Exynos4210UartState, 1,
|
||||||
vmstate_exynos4210_uart_fifo, Exynos4210UartFIFO),
|
vmstate_exynos4210_uart_fifo, Exynos4210UartFIFO),
|
||||||
|
|
|
@ -76,7 +76,6 @@ static const VMStateDescription vmstate_imx_serial = {
|
||||||
.name = "imx-serial",
|
.name = "imx-serial",
|
||||||
.version_id = 1,
|
.version_id = 1,
|
||||||
.minimum_version_id = 1,
|
.minimum_version_id = 1,
|
||||||
.minimum_version_id_old = 1,
|
|
||||||
.fields = (VMStateField[]) {
|
.fields = (VMStateField[]) {
|
||||||
VMSTATE_INT32(readbuff, IMXSerialState),
|
VMSTATE_INT32(readbuff, IMXSerialState),
|
||||||
VMSTATE_UINT32(usr1, IMXSerialState),
|
VMSTATE_UINT32(usr1, IMXSerialState),
|
||||||
|
|
|
@ -251,7 +251,6 @@ static const VMStateDescription vmstate_pl011 = {
|
||||||
.name = "pl011",
|
.name = "pl011",
|
||||||
.version_id = 2,
|
.version_id = 2,
|
||||||
.minimum_version_id = 2,
|
.minimum_version_id = 2,
|
||||||
.minimum_version_id_old = 2,
|
|
||||||
.fields = (VMStateField[]) {
|
.fields = (VMStateField[]) {
|
||||||
VMSTATE_UINT32(readbuff, PL011State),
|
VMSTATE_UINT32(readbuff, PL011State),
|
||||||
VMSTATE_UINT32(flags, PL011State),
|
VMSTATE_UINT32(flags, PL011State),
|
||||||
|
|
|
@ -121,7 +121,6 @@ static const VMStateDescription vmstate_ads7846 = {
|
||||||
.name = "ads7846",
|
.name = "ads7846",
|
||||||
.version_id = 1,
|
.version_id = 1,
|
||||||
.minimum_version_id = 1,
|
.minimum_version_id = 1,
|
||||||
.minimum_version_id_old = 1,
|
|
||||||
.post_load = ads7856_post_load,
|
.post_load = ads7856_post_load,
|
||||||
.fields = (VMStateField[]) {
|
.fields = (VMStateField[]) {
|
||||||
VMSTATE_SSI_SLAVE(ssidev, ADS7846State),
|
VMSTATE_SSI_SLAVE(ssidev, ADS7846State),
|
||||||
|
|
|
@ -932,7 +932,6 @@ static const VMStateDescription vmstate_dma_channel = {
|
||||||
.name = "dma_channel",
|
.name = "dma_channel",
|
||||||
.version_id = 0,
|
.version_id = 0,
|
||||||
.minimum_version_id = 0,
|
.minimum_version_id = 0,
|
||||||
.minimum_version_id_old = 0,
|
|
||||||
.fields = (VMStateField[]) {
|
.fields = (VMStateField[]) {
|
||||||
VMSTATE_UINT32(branch, struct DMAChannel),
|
VMSTATE_UINT32(branch, struct DMAChannel),
|
||||||
VMSTATE_UINT8(up, struct DMAChannel),
|
VMSTATE_UINT8(up, struct DMAChannel),
|
||||||
|
@ -959,7 +958,6 @@ static const VMStateDescription vmstate_pxa2xx_lcdc = {
|
||||||
.name = "pxa2xx_lcdc",
|
.name = "pxa2xx_lcdc",
|
||||||
.version_id = 0,
|
.version_id = 0,
|
||||||
.minimum_version_id = 0,
|
.minimum_version_id = 0,
|
||||||
.minimum_version_id_old = 0,
|
|
||||||
.post_load = pxa2xx_lcdc_post_load,
|
.post_load = pxa2xx_lcdc_post_load,
|
||||||
.fields = (VMStateField[]) {
|
.fields = (VMStateField[]) {
|
||||||
VMSTATE_INT32(irqlevel, PXA2xxLCDState),
|
VMSTATE_INT32(irqlevel, PXA2xxLCDState),
|
||||||
|
|
|
@ -272,8 +272,7 @@ static const VMStateDescription vmstate_ssd0303 = {
|
||||||
.name = "ssd0303_oled",
|
.name = "ssd0303_oled",
|
||||||
.version_id = 1,
|
.version_id = 1,
|
||||||
.minimum_version_id = 1,
|
.minimum_version_id = 1,
|
||||||
.minimum_version_id_old = 1,
|
.fields = (VMStateField[]) {
|
||||||
.fields = (VMStateField []) {
|
|
||||||
VMSTATE_INT32(row, ssd0303_state),
|
VMSTATE_INT32(row, ssd0303_state),
|
||||||
VMSTATE_INT32(col, ssd0303_state),
|
VMSTATE_INT32(col, ssd0303_state),
|
||||||
VMSTATE_INT32(start_line, ssd0303_state),
|
VMSTATE_INT32(start_line, ssd0303_state),
|
||||||
|
|
|
@ -973,7 +973,7 @@ static int omap_dma_ch_reg_write(struct omap_dma_s *s,
|
||||||
|
|
||||||
case 0x22: /* DMA_COLOR_U */
|
case 0x22: /* DMA_COLOR_U */
|
||||||
ch->color &= 0xffff;
|
ch->color &= 0xffff;
|
||||||
ch->color |= value << 16;
|
ch->color |= (uint32_t)value << 16;
|
||||||
break;
|
break;
|
||||||
|
|
||||||
case 0x24: /* DMA_CCR2 */
|
case 0x24: /* DMA_CCR2 */
|
||||||
|
@ -1043,7 +1043,7 @@ static int omap_dma_3_2_lcd_write(struct omap_dma_lcd_channel_s *s, int offset,
|
||||||
|
|
||||||
case 0xbca: /* TOP_B1_U */
|
case 0xbca: /* TOP_B1_U */
|
||||||
s->src_f1_top &= 0x0000ffff;
|
s->src_f1_top &= 0x0000ffff;
|
||||||
s->src_f1_top |= value << 16;
|
s->src_f1_top |= (uint32_t)value << 16;
|
||||||
break;
|
break;
|
||||||
|
|
||||||
case 0xbcc: /* BOT_B1_L */
|
case 0xbcc: /* BOT_B1_L */
|
||||||
|
@ -1265,7 +1265,7 @@ static int omap_dma_3_1_lcd_write(struct omap_dma_lcd_channel_s *s, int offset,
|
||||||
|
|
||||||
case 0x304: /* SYS_DMA_LCD_TOP_F1_U */
|
case 0x304: /* SYS_DMA_LCD_TOP_F1_U */
|
||||||
s->src_f1_top &= 0x0000ffff;
|
s->src_f1_top &= 0x0000ffff;
|
||||||
s->src_f1_top |= value << 16;
|
s->src_f1_top |= (uint32_t)value << 16;
|
||||||
break;
|
break;
|
||||||
|
|
||||||
case 0x306: /* SYS_DMA_LCD_BOT_F1_L */
|
case 0x306: /* SYS_DMA_LCD_BOT_F1_L */
|
||||||
|
@ -1275,7 +1275,7 @@ static int omap_dma_3_1_lcd_write(struct omap_dma_lcd_channel_s *s, int offset,
|
||||||
|
|
||||||
case 0x308: /* SYS_DMA_LCD_BOT_F1_U */
|
case 0x308: /* SYS_DMA_LCD_BOT_F1_U */
|
||||||
s->src_f1_bottom &= 0x0000ffff;
|
s->src_f1_bottom &= 0x0000ffff;
|
||||||
s->src_f1_bottom |= value << 16;
|
s->src_f1_bottom |= (uint32_t)value << 16;
|
||||||
break;
|
break;
|
||||||
|
|
||||||
case 0x30a: /* SYS_DMA_LCD_TOP_F2_L */
|
case 0x30a: /* SYS_DMA_LCD_TOP_F2_L */
|
||||||
|
@ -1285,7 +1285,7 @@ static int omap_dma_3_1_lcd_write(struct omap_dma_lcd_channel_s *s, int offset,
|
||||||
|
|
||||||
case 0x30c: /* SYS_DMA_LCD_TOP_F2_U */
|
case 0x30c: /* SYS_DMA_LCD_TOP_F2_U */
|
||||||
s->src_f2_top &= 0x0000ffff;
|
s->src_f2_top &= 0x0000ffff;
|
||||||
s->src_f2_top |= value << 16;
|
s->src_f2_top |= (uint32_t)value << 16;
|
||||||
break;
|
break;
|
||||||
|
|
||||||
case 0x30e: /* SYS_DMA_LCD_BOT_F2_L */
|
case 0x30e: /* SYS_DMA_LCD_BOT_F2_L */
|
||||||
|
@ -1295,7 +1295,7 @@ static int omap_dma_3_1_lcd_write(struct omap_dma_lcd_channel_s *s, int offset,
|
||||||
|
|
||||||
case 0x310: /* SYS_DMA_LCD_BOT_F2_U */
|
case 0x310: /* SYS_DMA_LCD_BOT_F2_U */
|
||||||
s->src_f2_bottom &= 0x0000ffff;
|
s->src_f2_bottom &= 0x0000ffff;
|
||||||
s->src_f2_bottom |= value << 16;
|
s->src_f2_bottom |= (uint32_t)value << 16;
|
||||||
break;
|
break;
|
||||||
|
|
||||||
default:
|
default:
|
||||||
|
|
|
@ -138,7 +138,6 @@ static const VMStateDescription vmstate_pl330_chan = {
|
||||||
.name = "pl330_chan",
|
.name = "pl330_chan",
|
||||||
.version_id = 1,
|
.version_id = 1,
|
||||||
.minimum_version_id = 1,
|
.minimum_version_id = 1,
|
||||||
.minimum_version_id_old = 1,
|
|
||||||
.fields = (VMStateField[]) {
|
.fields = (VMStateField[]) {
|
||||||
VMSTATE_UINT32(src, PL330Chan),
|
VMSTATE_UINT32(src, PL330Chan),
|
||||||
VMSTATE_UINT32(dst, PL330Chan),
|
VMSTATE_UINT32(dst, PL330Chan),
|
||||||
|
@ -170,7 +169,6 @@ static const VMStateDescription vmstate_pl330_fifo = {
|
||||||
.name = "pl330_chan",
|
.name = "pl330_chan",
|
||||||
.version_id = 1,
|
.version_id = 1,
|
||||||
.minimum_version_id = 1,
|
.minimum_version_id = 1,
|
||||||
.minimum_version_id_old = 1,
|
|
||||||
.fields = (VMStateField[]) {
|
.fields = (VMStateField[]) {
|
||||||
VMSTATE_VBUFFER_UINT32(buf, PL330Fifo, 1, NULL, 0, buf_size),
|
VMSTATE_VBUFFER_UINT32(buf, PL330Fifo, 1, NULL, 0, buf_size),
|
||||||
VMSTATE_VBUFFER_UINT32(tag, PL330Fifo, 1, NULL, 0, buf_size),
|
VMSTATE_VBUFFER_UINT32(tag, PL330Fifo, 1, NULL, 0, buf_size),
|
||||||
|
@ -195,7 +193,6 @@ static const VMStateDescription vmstate_pl330_queue_entry = {
|
||||||
.name = "pl330_queue_entry",
|
.name = "pl330_queue_entry",
|
||||||
.version_id = 1,
|
.version_id = 1,
|
||||||
.minimum_version_id = 1,
|
.minimum_version_id = 1,
|
||||||
.minimum_version_id_old = 1,
|
|
||||||
.fields = (VMStateField[]) {
|
.fields = (VMStateField[]) {
|
||||||
VMSTATE_UINT32(addr, PL330QueueEntry),
|
VMSTATE_UINT32(addr, PL330QueueEntry),
|
||||||
VMSTATE_UINT32(len, PL330QueueEntry),
|
VMSTATE_UINT32(len, PL330QueueEntry),
|
||||||
|
@ -218,7 +215,6 @@ static const VMStateDescription vmstate_pl330_queue = {
|
||||||
.name = "pl330_queue",
|
.name = "pl330_queue",
|
||||||
.version_id = 1,
|
.version_id = 1,
|
||||||
.minimum_version_id = 1,
|
.minimum_version_id = 1,
|
||||||
.minimum_version_id_old = 1,
|
|
||||||
.fields = (VMStateField[]) {
|
.fields = (VMStateField[]) {
|
||||||
VMSTATE_STRUCT_VARRAY_UINT32(queue, PL330Queue, queue_size, 1,
|
VMSTATE_STRUCT_VARRAY_UINT32(queue, PL330Queue, queue_size, 1,
|
||||||
vmstate_pl330_queue_entry, PL330QueueEntry),
|
vmstate_pl330_queue_entry, PL330QueueEntry),
|
||||||
|
@ -279,7 +275,6 @@ static const VMStateDescription vmstate_pl330 = {
|
||||||
.name = "pl330",
|
.name = "pl330",
|
||||||
.version_id = 1,
|
.version_id = 1,
|
||||||
.minimum_version_id = 1,
|
.minimum_version_id = 1,
|
||||||
.minimum_version_id_old = 1,
|
|
||||||
.fields = (VMStateField[]) {
|
.fields = (VMStateField[]) {
|
||||||
VMSTATE_STRUCT(manager, PL330State, 0, vmstate_pl330_chan, PL330Chan),
|
VMSTATE_STRUCT(manager, PL330State, 0, vmstate_pl330_chan, PL330Chan),
|
||||||
VMSTATE_STRUCT_VARRAY_UINT32(chan, PL330State, num_chnls, 0,
|
VMSTATE_STRUCT_VARRAY_UINT32(chan, PL330State, num_chnls, 0,
|
||||||
|
|
|
@ -514,7 +514,6 @@ static VMStateDescription vmstate_pxa2xx_dma_chan = {
|
||||||
.name = "pxa2xx_dma_chan",
|
.name = "pxa2xx_dma_chan",
|
||||||
.version_id = 1,
|
.version_id = 1,
|
||||||
.minimum_version_id = 1,
|
.minimum_version_id = 1,
|
||||||
.minimum_version_id_old = 1,
|
|
||||||
.fields = (VMStateField[]) {
|
.fields = (VMStateField[]) {
|
||||||
VMSTATE_UINT32(descr, PXA2xxDMAChannel),
|
VMSTATE_UINT32(descr, PXA2xxDMAChannel),
|
||||||
VMSTATE_UINT32(src, PXA2xxDMAChannel),
|
VMSTATE_UINT32(src, PXA2xxDMAChannel),
|
||||||
|
@ -530,7 +529,6 @@ static VMStateDescription vmstate_pxa2xx_dma = {
|
||||||
.name = "pxa2xx_dma",
|
.name = "pxa2xx_dma",
|
||||||
.version_id = 1,
|
.version_id = 1,
|
||||||
.minimum_version_id = 0,
|
.minimum_version_id = 0,
|
||||||
.minimum_version_id_old = 0,
|
|
||||||
.fields = (VMStateField[]) {
|
.fields = (VMStateField[]) {
|
||||||
VMSTATE_UNUSED_TEST(is_version_0, 4),
|
VMSTATE_UNUSED_TEST(is_version_0, 4),
|
||||||
VMSTATE_UINT32(stopintr, PXA2xxDMAState),
|
VMSTATE_UINT32(stopintr, PXA2xxDMAState),
|
||||||
|
|
|
@ -152,8 +152,7 @@ static const VMStateDescription vmstate_max7310 = {
|
||||||
.name = "max7310",
|
.name = "max7310",
|
||||||
.version_id = 0,
|
.version_id = 0,
|
||||||
.minimum_version_id = 0,
|
.minimum_version_id = 0,
|
||||||
.minimum_version_id_old = 0,
|
.fields = (VMStateField[]) {
|
||||||
.fields = (VMStateField []) {
|
|
||||||
VMSTATE_INT32(i2c_command_byte, MAX7310State),
|
VMSTATE_INT32(i2c_command_byte, MAX7310State),
|
||||||
VMSTATE_INT32(len, MAX7310State),
|
VMSTATE_INT32(len, MAX7310State),
|
||||||
VMSTATE_UINT8(level, MAX7310State),
|
VMSTATE_UINT8(level, MAX7310State),
|
||||||
|
|
|
@ -216,9 +216,8 @@ static const VMStateDescription vmstate_scoop_regs = {
|
||||||
.name = "scoop",
|
.name = "scoop",
|
||||||
.version_id = 1,
|
.version_id = 1,
|
||||||
.minimum_version_id = 0,
|
.minimum_version_id = 0,
|
||||||
.minimum_version_id_old = 0,
|
|
||||||
.post_load = scoop_post_load,
|
.post_load = scoop_post_load,
|
||||||
.fields = (VMStateField []) {
|
.fields = (VMStateField[]) {
|
||||||
VMSTATE_UINT16(status, ScoopInfo),
|
VMSTATE_UINT16(status, ScoopInfo),
|
||||||
VMSTATE_UINT16(power, ScoopInfo),
|
VMSTATE_UINT16(power, ScoopInfo),
|
||||||
VMSTATE_UINT32(gpio_level, ScoopInfo),
|
VMSTATE_UINT32(gpio_level, ScoopInfo),
|
||||||
|
|
|
@ -432,9 +432,8 @@ static const VMStateDescription vmstate_lm_kbd = {
|
||||||
.name = "LM8323",
|
.name = "LM8323",
|
||||||
.version_id = 0,
|
.version_id = 0,
|
||||||
.minimum_version_id = 0,
|
.minimum_version_id = 0,
|
||||||
.minimum_version_id_old = 0,
|
|
||||||
.post_load = lm_kbd_post_load,
|
.post_load = lm_kbd_post_load,
|
||||||
.fields = (VMStateField []) {
|
.fields = (VMStateField[]) {
|
||||||
VMSTATE_I2C_SLAVE(parent_obj, LM823KbdState),
|
VMSTATE_I2C_SLAVE(parent_obj, LM823KbdState),
|
||||||
VMSTATE_UINT8(i2c_dir, LM823KbdState),
|
VMSTATE_UINT8(i2c_dir, LM823KbdState),
|
||||||
VMSTATE_UINT8(i2c_cycle, LM823KbdState),
|
VMSTATE_UINT8(i2c_cycle, LM823KbdState),
|
||||||
|
|
|
@ -291,7 +291,6 @@ static const VMStateDescription vmstate_pxa2xx_keypad = {
|
||||||
.name = "pxa2xx_keypad",
|
.name = "pxa2xx_keypad",
|
||||||
.version_id = 0,
|
.version_id = 0,
|
||||||
.minimum_version_id = 0,
|
.minimum_version_id = 0,
|
||||||
.minimum_version_id_old = 0,
|
|
||||||
.fields = (VMStateField[]) {
|
.fields = (VMStateField[]) {
|
||||||
VMSTATE_UINT32(kpc, PXA2xxKeyPadState),
|
VMSTATE_UINT32(kpc, PXA2xxKeyPadState),
|
||||||
VMSTATE_UINT32(kpdk, PXA2xxKeyPadState),
|
VMSTATE_UINT32(kpdk, PXA2xxKeyPadState),
|
||||||
|
|
|
@ -51,7 +51,6 @@ static const VMStateDescription vmstate_stellaris_button = {
|
||||||
.name = "stellaris_button",
|
.name = "stellaris_button",
|
||||||
.version_id = 0,
|
.version_id = 0,
|
||||||
.minimum_version_id = 0,
|
.minimum_version_id = 0,
|
||||||
.minimum_version_id_old = 0,
|
|
||||||
.fields = (VMStateField[]) {
|
.fields = (VMStateField[]) {
|
||||||
VMSTATE_UINT8(pressed, gamepad_button),
|
VMSTATE_UINT8(pressed, gamepad_button),
|
||||||
VMSTATE_END_OF_LIST()
|
VMSTATE_END_OF_LIST()
|
||||||
|
@ -62,7 +61,6 @@ static const VMStateDescription vmstate_stellaris_gamepad = {
|
||||||
.name = "stellaris_gamepad",
|
.name = "stellaris_gamepad",
|
||||||
.version_id = 1,
|
.version_id = 1,
|
||||||
.minimum_version_id = 1,
|
.minimum_version_id = 1,
|
||||||
.minimum_version_id_old = 1,
|
|
||||||
.fields = (VMStateField[]) {
|
.fields = (VMStateField[]) {
|
||||||
VMSTATE_INT32(extension, gamepad_state),
|
VMSTATE_INT32(extension, gamepad_state),
|
||||||
VMSTATE_STRUCT_VARRAY_INT32(buttons, gamepad_state, num_buttons, 0,
|
VMSTATE_STRUCT_VARRAY_INT32(buttons, gamepad_state, num_buttons, 0,
|
||||||
|
|
|
@ -97,6 +97,7 @@ static void aw_a10_pic_write(void *opaque, hwaddr offset, uint64_t value,
|
||||||
switch (offset) {
|
switch (offset) {
|
||||||
case AW_A10_PIC_BASE_ADDR:
|
case AW_A10_PIC_BASE_ADDR:
|
||||||
s->base_addr = value & ~0x3;
|
s->base_addr = value & ~0x3;
|
||||||
|
break;
|
||||||
case AW_A10_PIC_PROTECT:
|
case AW_A10_PIC_PROTECT:
|
||||||
s->protect = value;
|
s->protect = value;
|
||||||
break;
|
break;
|
||||||
|
@ -141,7 +142,6 @@ static const VMStateDescription vmstate_aw_a10_pic = {
|
||||||
.name = "a10.pic",
|
.name = "a10.pic",
|
||||||
.version_id = 1,
|
.version_id = 1,
|
||||||
.minimum_version_id = 1,
|
.minimum_version_id = 1,
|
||||||
.minimum_version_id_old = 1,
|
|
||||||
.fields = (VMStateField[]) {
|
.fields = (VMStateField[]) {
|
||||||
VMSTATE_UINT32(vector, AwA10PICState),
|
VMSTATE_UINT32(vector, AwA10PICState),
|
||||||
VMSTATE_UINT32(base_addr, AwA10PICState),
|
VMSTATE_UINT32(base_addr, AwA10PICState),
|
||||||
|
|
|
@ -443,7 +443,6 @@ static const VMStateDescription vmstate_nvic = {
|
||||||
.name = "armv7m_nvic",
|
.name = "armv7m_nvic",
|
||||||
.version_id = 1,
|
.version_id = 1,
|
||||||
.minimum_version_id = 1,
|
.minimum_version_id = 1,
|
||||||
.minimum_version_id_old = 1,
|
|
||||||
.fields = (VMStateField[]) {
|
.fields = (VMStateField[]) {
|
||||||
VMSTATE_UINT32(systick.control, nvic_state),
|
VMSTATE_UINT32(systick.control, nvic_state),
|
||||||
VMSTATE_UINT32(systick.reload, nvic_state),
|
VMSTATE_UINT32(systick.reload, nvic_state),
|
||||||
|
|
|
@ -77,7 +77,6 @@ static const VMStateDescription vmstate_exynos4210_combiner_group_state = {
|
||||||
.name = "exynos4210.combiner.groupstate",
|
.name = "exynos4210.combiner.groupstate",
|
||||||
.version_id = 1,
|
.version_id = 1,
|
||||||
.minimum_version_id = 1,
|
.minimum_version_id = 1,
|
||||||
.minimum_version_id_old = 1,
|
|
||||||
.fields = (VMStateField[]) {
|
.fields = (VMStateField[]) {
|
||||||
VMSTATE_UINT8(src_mask, CombinerGroupState),
|
VMSTATE_UINT8(src_mask, CombinerGroupState),
|
||||||
VMSTATE_UINT8(src_pending, CombinerGroupState),
|
VMSTATE_UINT8(src_pending, CombinerGroupState),
|
||||||
|
@ -89,7 +88,6 @@ static const VMStateDescription vmstate_exynos4210_combiner = {
|
||||||
.name = "exynos4210.combiner",
|
.name = "exynos4210.combiner",
|
||||||
.version_id = 1,
|
.version_id = 1,
|
||||||
.minimum_version_id = 1,
|
.minimum_version_id = 1,
|
||||||
.minimum_version_id_old = 1,
|
|
||||||
.fields = (VMStateField[]) {
|
.fields = (VMStateField[]) {
|
||||||
VMSTATE_STRUCT_ARRAY(group, Exynos4210CombinerState, IIC_NGRP, 0,
|
VMSTATE_STRUCT_ARRAY(group, Exynos4210CombinerState, IIC_NGRP, 0,
|
||||||
vmstate_exynos4210_combiner_group_state, CombinerGroupState),
|
vmstate_exynos4210_combiner_group_state, CombinerGroupState),
|
||||||
|
|
|
@ -394,7 +394,6 @@ static const VMStateDescription vmstate_exynos4210_irq_gate = {
|
||||||
.name = "exynos4210.irq_gate",
|
.name = "exynos4210.irq_gate",
|
||||||
.version_id = 2,
|
.version_id = 2,
|
||||||
.minimum_version_id = 2,
|
.minimum_version_id = 2,
|
||||||
.minimum_version_id_old = 2,
|
|
||||||
.fields = (VMStateField[]) {
|
.fields = (VMStateField[]) {
|
||||||
VMSTATE_VBUFFER_UINT32(level, Exynos4210IRQGateState, 1, NULL, 0, n_in),
|
VMSTATE_VBUFFER_UINT32(level, Exynos4210IRQGateState, 1, NULL, 0, n_in),
|
||||||
VMSTATE_END_OF_LIST()
|
VMSTATE_END_OF_LIST()
|
||||||
|
|
|
@ -77,7 +77,6 @@ static const VMStateDescription vmstate_imx_avic = {
|
||||||
.name = "imx-avic",
|
.name = "imx-avic",
|
||||||
.version_id = 1,
|
.version_id = 1,
|
||||||
.minimum_version_id = 1,
|
.minimum_version_id = 1,
|
||||||
.minimum_version_id_old = 1,
|
|
||||||
.fields = (VMStateField[]) {
|
.fields = (VMStateField[]) {
|
||||||
VMSTATE_UINT64(pending, IMXAVICState),
|
VMSTATE_UINT64(pending, IMXAVICState),
|
||||||
VMSTATE_UINT64(enabled, IMXAVICState),
|
VMSTATE_UINT64(enabled, IMXAVICState),
|
||||||
|
|
|
@ -57,7 +57,6 @@ static const VMStateDescription vmstate_imx_ccm = {
|
||||||
.name = "imx-ccm",
|
.name = "imx-ccm",
|
||||||
.version_id = 1,
|
.version_id = 1,
|
||||||
.minimum_version_id = 1,
|
.minimum_version_id = 1,
|
||||||
.minimum_version_id_old = 1,
|
|
||||||
.fields = (VMStateField[]) {
|
.fields = (VMStateField[]) {
|
||||||
VMSTATE_UINT32(ccmr, IMXCCMState),
|
VMSTATE_UINT32(ccmr, IMXCCMState),
|
||||||
VMSTATE_UINT32(pdr0, IMXCCMState),
|
VMSTATE_UINT32(pdr0, IMXCCMState),
|
||||||
|
|
|
@ -110,7 +110,6 @@ static const VMStateDescription vmstate_max111x = {
|
||||||
.name = "max111x",
|
.name = "max111x",
|
||||||
.version_id = 1,
|
.version_id = 1,
|
||||||
.minimum_version_id = 1,
|
.minimum_version_id = 1,
|
||||||
.minimum_version_id_old = 1,
|
|
||||||
.fields = (VMStateField[]) {
|
.fields = (VMStateField[]) {
|
||||||
VMSTATE_SSI_SLAVE(parent_obj, MAX111xState),
|
VMSTATE_SSI_SLAVE(parent_obj, MAX111xState),
|
||||||
VMSTATE_UINT8(tb1, MAX111xState),
|
VMSTATE_UINT8(tb1, MAX111xState),
|
||||||
|
|
|
@ -222,9 +222,8 @@ static VMStateDescription vmstate_mst_fpga_regs = {
|
||||||
.name = "mainstone_fpga",
|
.name = "mainstone_fpga",
|
||||||
.version_id = 0,
|
.version_id = 0,
|
||||||
.minimum_version_id = 0,
|
.minimum_version_id = 0,
|
||||||
.minimum_version_id_old = 0,
|
|
||||||
.post_load = mst_fpga_post_load,
|
.post_load = mst_fpga_post_load,
|
||||||
.fields = (VMStateField []) {
|
.fields = (VMStateField[]) {
|
||||||
VMSTATE_UINT32(prev_level, mst_irq_state),
|
VMSTATE_UINT32(prev_level, mst_irq_state),
|
||||||
VMSTATE_UINT32(leddat1, mst_irq_state),
|
VMSTATE_UINT32(leddat1, mst_irq_state),
|
||||||
VMSTATE_UINT32(leddat2, mst_irq_state),
|
VMSTATE_UINT32(leddat2, mst_irq_state),
|
||||||
|
|
|
@ -242,6 +242,10 @@ static void fill_prefetch_fifo(struct omap_gpmc_s *s)
|
||||||
if (bytes > s->prefetch.count) {
|
if (bytes > s->prefetch.count) {
|
||||||
bytes = s->prefetch.count;
|
bytes = s->prefetch.count;
|
||||||
}
|
}
|
||||||
|
if (is16bit) {
|
||||||
|
bytes &= ~1;
|
||||||
|
}
|
||||||
|
|
||||||
s->prefetch.count -= bytes;
|
s->prefetch.count -= bytes;
|
||||||
s->prefetch.fifopointer += bytes;
|
s->prefetch.fifopointer += bytes;
|
||||||
fptr = 64 - s->prefetch.fifopointer;
|
fptr = 64 - s->prefetch.fifopointer;
|
||||||
|
|
|
@ -199,9 +199,8 @@ static const VMStateDescription vmstate_tmp105 = {
|
||||||
.name = "TMP105",
|
.name = "TMP105",
|
||||||
.version_id = 0,
|
.version_id = 0,
|
||||||
.minimum_version_id = 0,
|
.minimum_version_id = 0,
|
||||||
.minimum_version_id_old = 0,
|
|
||||||
.post_load = tmp105_post_load,
|
.post_load = tmp105_post_load,
|
||||||
.fields = (VMStateField []) {
|
.fields = (VMStateField[]) {
|
||||||
VMSTATE_UINT8(len, TMP105State),
|
VMSTATE_UINT8(len, TMP105State),
|
||||||
VMSTATE_UINT8_ARRAY(buf, TMP105State, 2),
|
VMSTATE_UINT8_ARRAY(buf, TMP105State, 2),
|
||||||
VMSTATE_UINT8(pointer, TMP105State),
|
VMSTATE_UINT8(pointer, TMP105State),
|
||||||
|
|
|
@ -428,7 +428,6 @@ static const VMStateDescription vmstate_zynq_slcr = {
|
||||||
.name = "zynq_slcr",
|
.name = "zynq_slcr",
|
||||||
.version_id = 2,
|
.version_id = 2,
|
||||||
.minimum_version_id = 2,
|
.minimum_version_id = 2,
|
||||||
.minimum_version_id_old = 2,
|
|
||||||
.fields = (VMStateField[]) {
|
.fields = (VMStateField[]) {
|
||||||
VMSTATE_UINT32_ARRAY(regs, ZynqSLCRState, ZYNQ_SLCR_NUM_REGS),
|
VMSTATE_UINT32_ARRAY(regs, ZynqSLCRState, ZYNQ_SLCR_NUM_REGS),
|
||||||
VMSTATE_END_OF_LIST()
|
VMSTATE_END_OF_LIST()
|
||||||
|
|
|
@ -717,7 +717,6 @@ static ssize_t gem_receive(NetClientState *nc, const uint8_t *buf, size_t size)
|
||||||
rxbuf_ptr = (void *)buf;
|
rxbuf_ptr = (void *)buf;
|
||||||
} else {
|
} else {
|
||||||
unsigned crc_val;
|
unsigned crc_val;
|
||||||
int crc_offset;
|
|
||||||
|
|
||||||
/* The application wants the FCS field, which QEMU does not provide.
|
/* The application wants the FCS field, which QEMU does not provide.
|
||||||
* We must try and caclculate one.
|
* We must try and caclculate one.
|
||||||
|
@ -727,12 +726,7 @@ static ssize_t gem_receive(NetClientState *nc, const uint8_t *buf, size_t size)
|
||||||
memset(rxbuf + size, 0, sizeof(rxbuf) - size);
|
memset(rxbuf + size, 0, sizeof(rxbuf) - size);
|
||||||
rxbuf_ptr = rxbuf;
|
rxbuf_ptr = rxbuf;
|
||||||
crc_val = cpu_to_le32(crc32(0, rxbuf, MAX(size, 60)));
|
crc_val = cpu_to_le32(crc32(0, rxbuf, MAX(size, 60)));
|
||||||
if (size < 60) {
|
memcpy(rxbuf + size, &crc_val, sizeof(crc_val));
|
||||||
crc_offset = 60;
|
|
||||||
} else {
|
|
||||||
crc_offset = size;
|
|
||||||
}
|
|
||||||
memcpy(rxbuf + crc_offset, &crc_val, sizeof(crc_val));
|
|
||||||
|
|
||||||
bytes_to_copy += 4;
|
bytes_to_copy += 4;
|
||||||
size += 4;
|
size += 4;
|
||||||
|
@ -1257,7 +1251,6 @@ static const VMStateDescription vmstate_cadence_gem = {
|
||||||
.name = "cadence_gem",
|
.name = "cadence_gem",
|
||||||
.version_id = 2,
|
.version_id = 2,
|
||||||
.minimum_version_id = 2,
|
.minimum_version_id = 2,
|
||||||
.minimum_version_id_old = 2,
|
|
||||||
.fields = (VMStateField[]) {
|
.fields = (VMStateField[]) {
|
||||||
VMSTATE_UINT32_ARRAY(regs, GemState, GEM_MAXREG),
|
VMSTATE_UINT32_ARRAY(regs, GemState, GEM_MAXREG),
|
||||||
VMSTATE_UINT16_ARRAY(phy_regs, GemState, 32),
|
VMSTATE_UINT16_ARRAY(phy_regs, GemState, 32),
|
||||||
|
|
|
@ -54,7 +54,7 @@ static const VMStateDescription vmstate_smc91c111 = {
|
||||||
.name = "smc91c111",
|
.name = "smc91c111",
|
||||||
.version_id = 1,
|
.version_id = 1,
|
||||||
.minimum_version_id = 1,
|
.minimum_version_id = 1,
|
||||||
.fields = (VMStateField []) {
|
.fields = (VMStateField[]) {
|
||||||
VMSTATE_UINT16(tcr, smc91c111_state),
|
VMSTATE_UINT16(tcr, smc91c111_state),
|
||||||
VMSTATE_UINT16(rcr, smc91c111_state),
|
VMSTATE_UINT16(rcr, smc91c111_state),
|
||||||
VMSTATE_UINT16(cr, smc91c111_state),
|
VMSTATE_UINT16(cr, smc91c111_state),
|
||||||
|
|
|
@ -46,6 +46,11 @@ do { fprintf(stderr, "stellaris_enet: error: " fmt , ## __VA_ARGS__);} while (0)
|
||||||
#define STELLARIS_ENET(obj) \
|
#define STELLARIS_ENET(obj) \
|
||||||
OBJECT_CHECK(stellaris_enet_state, (obj), TYPE_STELLARIS_ENET)
|
OBJECT_CHECK(stellaris_enet_state, (obj), TYPE_STELLARIS_ENET)
|
||||||
|
|
||||||
|
typedef struct {
|
||||||
|
uint8_t data[2048];
|
||||||
|
uint32_t len;
|
||||||
|
} StellarisEnetRxFrame;
|
||||||
|
|
||||||
typedef struct {
|
typedef struct {
|
||||||
SysBusDevice parent_obj;
|
SysBusDevice parent_obj;
|
||||||
|
|
||||||
|
@ -59,29 +64,159 @@ typedef struct {
|
||||||
uint32_t mtxd;
|
uint32_t mtxd;
|
||||||
uint32_t mrxd;
|
uint32_t mrxd;
|
||||||
uint32_t np;
|
uint32_t np;
|
||||||
int tx_frame_len;
|
uint32_t tx_fifo_len;
|
||||||
int tx_fifo_len;
|
|
||||||
uint8_t tx_fifo[2048];
|
uint8_t tx_fifo[2048];
|
||||||
/* Real hardware has a 2k fifo, which works out to be at most 31 packets.
|
/* Real hardware has a 2k fifo, which works out to be at most 31 packets.
|
||||||
We implement a full 31 packet fifo. */
|
We implement a full 31 packet fifo. */
|
||||||
struct {
|
StellarisEnetRxFrame rx[31];
|
||||||
uint8_t data[2048];
|
uint32_t rx_fifo_offset;
|
||||||
int len;
|
uint32_t next_packet;
|
||||||
} rx[31];
|
|
||||||
uint8_t *rx_fifo;
|
|
||||||
int rx_fifo_len;
|
|
||||||
int next_packet;
|
|
||||||
NICState *nic;
|
NICState *nic;
|
||||||
NICConf conf;
|
NICConf conf;
|
||||||
qemu_irq irq;
|
qemu_irq irq;
|
||||||
MemoryRegion mmio;
|
MemoryRegion mmio;
|
||||||
} stellaris_enet_state;
|
} stellaris_enet_state;
|
||||||
|
|
||||||
|
static const VMStateDescription vmstate_rx_frame = {
|
||||||
|
.name = "stellaris_enet/rx_frame",
|
||||||
|
.version_id = 1,
|
||||||
|
.minimum_version_id = 1,
|
||||||
|
.fields = (VMStateField[]) {
|
||||||
|
VMSTATE_UINT8_ARRAY(data, StellarisEnetRxFrame, 2048),
|
||||||
|
VMSTATE_UINT32(len, StellarisEnetRxFrame),
|
||||||
|
VMSTATE_END_OF_LIST()
|
||||||
|
}
|
||||||
|
};
|
||||||
|
|
||||||
|
static int stellaris_enet_post_load(void *opaque, int version_id)
|
||||||
|
{
|
||||||
|
stellaris_enet_state *s = opaque;
|
||||||
|
int i;
|
||||||
|
|
||||||
|
/* Sanitize inbound state. Note that next_packet is an index but
|
||||||
|
* np is a size; hence their valid upper bounds differ.
|
||||||
|
*/
|
||||||
|
if (s->next_packet >= ARRAY_SIZE(s->rx)) {
|
||||||
|
return -1;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (s->np > ARRAY_SIZE(s->rx)) {
|
||||||
|
return -1;
|
||||||
|
}
|
||||||
|
|
||||||
|
for (i = 0; i < ARRAY_SIZE(s->rx); i++) {
|
||||||
|
if (s->rx[i].len > ARRAY_SIZE(s->rx[i].data)) {
|
||||||
|
return -1;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
if (s->rx_fifo_offset > ARRAY_SIZE(s->rx[0].data) - 4) {
|
||||||
|
return -1;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (s->tx_fifo_len > ARRAY_SIZE(s->tx_fifo)) {
|
||||||
|
return -1;
|
||||||
|
}
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
static const VMStateDescription vmstate_stellaris_enet = {
|
||||||
|
.name = "stellaris_enet",
|
||||||
|
.version_id = 2,
|
||||||
|
.minimum_version_id = 2,
|
||||||
|
.post_load = stellaris_enet_post_load,
|
||||||
|
.fields = (VMStateField[]) {
|
||||||
|
VMSTATE_UINT32(ris, stellaris_enet_state),
|
||||||
|
VMSTATE_UINT32(im, stellaris_enet_state),
|
||||||
|
VMSTATE_UINT32(rctl, stellaris_enet_state),
|
||||||
|
VMSTATE_UINT32(tctl, stellaris_enet_state),
|
||||||
|
VMSTATE_UINT32(thr, stellaris_enet_state),
|
||||||
|
VMSTATE_UINT32(mctl, stellaris_enet_state),
|
||||||
|
VMSTATE_UINT32(mdv, stellaris_enet_state),
|
||||||
|
VMSTATE_UINT32(mtxd, stellaris_enet_state),
|
||||||
|
VMSTATE_UINT32(mrxd, stellaris_enet_state),
|
||||||
|
VMSTATE_UINT32(np, stellaris_enet_state),
|
||||||
|
VMSTATE_UINT32(tx_fifo_len, stellaris_enet_state),
|
||||||
|
VMSTATE_UINT8_ARRAY(tx_fifo, stellaris_enet_state, 2048),
|
||||||
|
VMSTATE_STRUCT_ARRAY(rx, stellaris_enet_state, 31, 1,
|
||||||
|
vmstate_rx_frame, StellarisEnetRxFrame),
|
||||||
|
VMSTATE_UINT32(rx_fifo_offset, stellaris_enet_state),
|
||||||
|
VMSTATE_UINT32(next_packet, stellaris_enet_state),
|
||||||
|
VMSTATE_END_OF_LIST()
|
||||||
|
}
|
||||||
|
};
|
||||||
|
|
||||||
static void stellaris_enet_update(stellaris_enet_state *s)
|
static void stellaris_enet_update(stellaris_enet_state *s)
|
||||||
{
|
{
|
||||||
qemu_set_irq(s->irq, (s->ris & s->im) != 0);
|
qemu_set_irq(s->irq, (s->ris & s->im) != 0);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
/* Return the data length of the packet currently being assembled
|
||||||
|
* in the TX fifo.
|
||||||
|
*/
|
||||||
|
static inline int stellaris_txpacket_datalen(stellaris_enet_state *s)
|
||||||
|
{
|
||||||
|
return s->tx_fifo[0] | (s->tx_fifo[1] << 8);
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Return true if the packet currently in the TX FIFO is complete,
|
||||||
|
* ie the FIFO holds enough bytes for the data length, ethernet header,
|
||||||
|
* payload and optionally CRC.
|
||||||
|
*/
|
||||||
|
static inline bool stellaris_txpacket_complete(stellaris_enet_state *s)
|
||||||
|
{
|
||||||
|
int framelen = stellaris_txpacket_datalen(s);
|
||||||
|
framelen += 16;
|
||||||
|
if (!(s->tctl & SE_TCTL_CRC)) {
|
||||||
|
framelen += 4;
|
||||||
|
}
|
||||||
|
/* Cover the corner case of a 2032 byte payload with auto-CRC disabled:
|
||||||
|
* this requires more bytes than will fit in the FIFO. It's not totally
|
||||||
|
* clear how the h/w handles this, but if using threshold-based TX
|
||||||
|
* it will definitely try to transmit something.
|
||||||
|
*/
|
||||||
|
framelen = MIN(framelen, ARRAY_SIZE(s->tx_fifo));
|
||||||
|
return s->tx_fifo_len >= framelen;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Return true if the TX FIFO threshold is enabled and the FIFO
|
||||||
|
* has filled enough to reach it.
|
||||||
|
*/
|
||||||
|
static inline bool stellaris_tx_thr_reached(stellaris_enet_state *s)
|
||||||
|
{
|
||||||
|
return (s->thr < 0x3f &&
|
||||||
|
(s->tx_fifo_len >= 4 * (s->thr * 8 + 1)));
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Send the packet currently in the TX FIFO */
|
||||||
|
static void stellaris_enet_send(stellaris_enet_state *s)
|
||||||
|
{
|
||||||
|
int framelen = stellaris_txpacket_datalen(s);
|
||||||
|
|
||||||
|
/* Ethernet header is in the FIFO but not in the datacount.
|
||||||
|
* We don't implement explicit CRC, so just ignore any
|
||||||
|
* CRC value in the FIFO.
|
||||||
|
*/
|
||||||
|
framelen += 14;
|
||||||
|
if ((s->tctl & SE_TCTL_PADEN) && framelen < 60) {
|
||||||
|
memset(&s->tx_fifo[framelen + 2], 0, 60 - framelen);
|
||||||
|
framelen = 60;
|
||||||
|
}
|
||||||
|
/* This MIN will have no effect unless the FIFO data is corrupt
|
||||||
|
* (eg bad data from an incoming migration); otherwise the check
|
||||||
|
* on the datalen at the start of writing the data into the FIFO
|
||||||
|
* will have caught this. Silently write a corrupt half-packet,
|
||||||
|
* which is what the hardware does in FIFO underrun situations.
|
||||||
|
*/
|
||||||
|
framelen = MIN(framelen, ARRAY_SIZE(s->tx_fifo) - 2);
|
||||||
|
qemu_send_packet(qemu_get_queue(s->nic), s->tx_fifo + 2, framelen);
|
||||||
|
s->tx_fifo_len = 0;
|
||||||
|
s->ris |= SE_INT_TXEMP;
|
||||||
|
stellaris_enet_update(s);
|
||||||
|
DPRINTF("Done TX\n");
|
||||||
|
}
|
||||||
|
|
||||||
/* TODO: Implement MAC address filtering. */
|
/* TODO: Implement MAC address filtering. */
|
||||||
static ssize_t stellaris_enet_receive(NetClientState *nc, const uint8_t *buf, size_t size)
|
static ssize_t stellaris_enet_receive(NetClientState *nc, const uint8_t *buf, size_t size)
|
||||||
{
|
{
|
||||||
|
@ -97,7 +232,7 @@ static ssize_t stellaris_enet_receive(NetClientState *nc, const uint8_t *buf, si
|
||||||
return -1;
|
return -1;
|
||||||
}
|
}
|
||||||
|
|
||||||
DPRINTF("Received packet len=%d\n", size);
|
DPRINTF("Received packet len=%zu\n", size);
|
||||||
n = s->next_packet + s->np;
|
n = s->next_packet + s->np;
|
||||||
if (n >= 31)
|
if (n >= 31)
|
||||||
n -= 31;
|
n -= 31;
|
||||||
|
@ -152,21 +287,21 @@ static uint64_t stellaris_enet_read(void *opaque, hwaddr offset,
|
||||||
case 0x0c: /* TCTL */
|
case 0x0c: /* TCTL */
|
||||||
return s->tctl;
|
return s->tctl;
|
||||||
case 0x10: /* DATA */
|
case 0x10: /* DATA */
|
||||||
if (s->rx_fifo_len == 0) {
|
{
|
||||||
|
uint8_t *rx_fifo;
|
||||||
|
|
||||||
if (s->np == 0) {
|
if (s->np == 0) {
|
||||||
BADF("RX underflow\n");
|
BADF("RX underflow\n");
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
s->rx_fifo_len = s->rx[s->next_packet].len;
|
|
||||||
s->rx_fifo = s->rx[s->next_packet].data;
|
rx_fifo = s->rx[s->next_packet].data + s->rx_fifo_offset;
|
||||||
DPRINTF("RX FIFO start packet len=%d\n", s->rx_fifo_len);
|
|
||||||
}
|
val = rx_fifo[0] | (rx_fifo[1] << 8) | (rx_fifo[2] << 16)
|
||||||
val = s->rx_fifo[0] | (s->rx_fifo[1] << 8) | (s->rx_fifo[2] << 16)
|
| (rx_fifo[3] << 24);
|
||||||
| (s->rx_fifo[3] << 24);
|
s->rx_fifo_offset += 4;
|
||||||
s->rx_fifo += 4;
|
if (s->rx_fifo_offset >= s->rx[s->next_packet].len) {
|
||||||
s->rx_fifo_len -= 4;
|
s->rx_fifo_offset = 0;
|
||||||
if (s->rx_fifo_len <= 0) {
|
|
||||||
s->rx_fifo_len = 0;
|
|
||||||
s->next_packet++;
|
s->next_packet++;
|
||||||
if (s->next_packet >= 31)
|
if (s->next_packet >= 31)
|
||||||
s->next_packet = 0;
|
s->next_packet = 0;
|
||||||
|
@ -174,6 +309,7 @@ static uint64_t stellaris_enet_read(void *opaque, hwaddr offset,
|
||||||
DPRINTF("RX done np=%d\n", s->np);
|
DPRINTF("RX done np=%d\n", s->np);
|
||||||
}
|
}
|
||||||
return val;
|
return val;
|
||||||
|
}
|
||||||
case 0x14: /* IA0 */
|
case 0x14: /* IA0 */
|
||||||
return s->conf.macaddr.a[0] | (s->conf.macaddr.a[1] << 8)
|
return s->conf.macaddr.a[0] | (s->conf.macaddr.a[1] << 8)
|
||||||
| (s->conf.macaddr.a[2] << 16)
|
| (s->conf.macaddr.a[2] << 16)
|
||||||
|
@ -212,22 +348,23 @@ static void stellaris_enet_write(void *opaque, hwaddr offset,
|
||||||
switch (offset) {
|
switch (offset) {
|
||||||
case 0x00: /* IACK */
|
case 0x00: /* IACK */
|
||||||
s->ris &= ~value;
|
s->ris &= ~value;
|
||||||
DPRINTF("IRQ ack %02x/%02x\n", value, s->ris);
|
DPRINTF("IRQ ack %02" PRIx64 "/%02x\n", value, s->ris);
|
||||||
stellaris_enet_update(s);
|
stellaris_enet_update(s);
|
||||||
/* Clearing TXER also resets the TX fifo. */
|
/* Clearing TXER also resets the TX fifo. */
|
||||||
if (value & SE_INT_TXER)
|
if (value & SE_INT_TXER) {
|
||||||
s->tx_frame_len = -1;
|
s->tx_fifo_len = 0;
|
||||||
|
}
|
||||||
break;
|
break;
|
||||||
case 0x04: /* IM */
|
case 0x04: /* IM */
|
||||||
DPRINTF("IRQ mask %02x/%02x\n", value, s->ris);
|
DPRINTF("IRQ mask %02" PRIx64 "/%02x\n", value, s->ris);
|
||||||
s->im = value;
|
s->im = value;
|
||||||
stellaris_enet_update(s);
|
stellaris_enet_update(s);
|
||||||
break;
|
break;
|
||||||
case 0x08: /* RCTL */
|
case 0x08: /* RCTL */
|
||||||
s->rctl = value;
|
s->rctl = value;
|
||||||
if (value & SE_RCTL_RSTFIFO) {
|
if (value & SE_RCTL_RSTFIFO) {
|
||||||
s->rx_fifo_len = 0;
|
|
||||||
s->np = 0;
|
s->np = 0;
|
||||||
|
s->rx_fifo_offset = 0;
|
||||||
stellaris_enet_update(s);
|
stellaris_enet_update(s);
|
||||||
}
|
}
|
||||||
break;
|
break;
|
||||||
|
@ -235,43 +372,26 @@ static void stellaris_enet_write(void *opaque, hwaddr offset,
|
||||||
s->tctl = value;
|
s->tctl = value;
|
||||||
break;
|
break;
|
||||||
case 0x10: /* DATA */
|
case 0x10: /* DATA */
|
||||||
if (s->tx_frame_len == -1) {
|
if (s->tx_fifo_len == 0) {
|
||||||
s->tx_frame_len = value & 0xffff;
|
/* The first word is special, it contains the data length */
|
||||||
if (s->tx_frame_len > 2032) {
|
int framelen = value & 0xffff;
|
||||||
DPRINTF("TX frame too long (%d)\n", s->tx_frame_len);
|
if (framelen > 2032) {
|
||||||
s->tx_frame_len = 0;
|
DPRINTF("TX frame too long (%d)\n", framelen);
|
||||||
s->ris |= SE_INT_TXER;
|
s->ris |= SE_INT_TXER;
|
||||||
stellaris_enet_update(s);
|
stellaris_enet_update(s);
|
||||||
} else {
|
break;
|
||||||
DPRINTF("Start TX frame len=%d\n", s->tx_frame_len);
|
|
||||||
/* The value written does not include the ethernet header. */
|
|
||||||
s->tx_frame_len += 14;
|
|
||||||
if ((s->tctl & SE_TCTL_CRC) == 0)
|
|
||||||
s->tx_frame_len += 4;
|
|
||||||
s->tx_fifo_len = 0;
|
|
||||||
s->tx_fifo[s->tx_fifo_len++] = value >> 16;
|
|
||||||
s->tx_fifo[s->tx_fifo_len++] = value >> 24;
|
|
||||||
}
|
}
|
||||||
} else {
|
}
|
||||||
|
|
||||||
|
if (s->tx_fifo_len + 4 <= ARRAY_SIZE(s->tx_fifo)) {
|
||||||
s->tx_fifo[s->tx_fifo_len++] = value;
|
s->tx_fifo[s->tx_fifo_len++] = value;
|
||||||
s->tx_fifo[s->tx_fifo_len++] = value >> 8;
|
s->tx_fifo[s->tx_fifo_len++] = value >> 8;
|
||||||
s->tx_fifo[s->tx_fifo_len++] = value >> 16;
|
s->tx_fifo[s->tx_fifo_len++] = value >> 16;
|
||||||
s->tx_fifo[s->tx_fifo_len++] = value >> 24;
|
s->tx_fifo[s->tx_fifo_len++] = value >> 24;
|
||||||
if (s->tx_fifo_len >= s->tx_frame_len) {
|
|
||||||
/* We don't implement explicit CRC, so just chop it off. */
|
|
||||||
if ((s->tctl & SE_TCTL_CRC) == 0)
|
|
||||||
s->tx_frame_len -= 4;
|
|
||||||
if ((s->tctl & SE_TCTL_PADEN) && s->tx_frame_len < 60) {
|
|
||||||
memset(&s->tx_fifo[s->tx_frame_len], 0, 60 - s->tx_frame_len);
|
|
||||||
s->tx_fifo_len = 60;
|
|
||||||
}
|
|
||||||
qemu_send_packet(qemu_get_queue(s->nic), s->tx_fifo,
|
|
||||||
s->tx_frame_len);
|
|
||||||
s->tx_frame_len = -1;
|
|
||||||
s->ris |= SE_INT_TXEMP;
|
|
||||||
stellaris_enet_update(s);
|
|
||||||
DPRINTF("Done TX\n");
|
|
||||||
}
|
}
|
||||||
|
|
||||||
|
if (stellaris_tx_thr_reached(s) && stellaris_txpacket_complete(s)) {
|
||||||
|
stellaris_enet_send(s);
|
||||||
}
|
}
|
||||||
break;
|
break;
|
||||||
case 0x14: /* IA0 */
|
case 0x14: /* IA0 */
|
||||||
|
@ -299,9 +419,13 @@ static void stellaris_enet_write(void *opaque, hwaddr offset,
|
||||||
case 0x2c: /* MTXD */
|
case 0x2c: /* MTXD */
|
||||||
s->mtxd = value & 0xff;
|
s->mtxd = value & 0xff;
|
||||||
break;
|
break;
|
||||||
|
case 0x38: /* TR */
|
||||||
|
if (value & 1) {
|
||||||
|
stellaris_enet_send(s);
|
||||||
|
}
|
||||||
|
break;
|
||||||
case 0x30: /* MRXD */
|
case 0x30: /* MRXD */
|
||||||
case 0x34: /* NP */
|
case 0x34: /* NP */
|
||||||
case 0x38: /* TR */
|
|
||||||
/* Ignored. */
|
/* Ignored. */
|
||||||
case 0x3c: /* Undocuented: Timestamp? */
|
case 0x3c: /* Undocuented: Timestamp? */
|
||||||
/* Ignored. */
|
/* Ignored. */
|
||||||
|
@ -324,68 +448,7 @@ static void stellaris_enet_reset(stellaris_enet_state *s)
|
||||||
s->im = SE_INT_PHY | SE_INT_MD | SE_INT_RXER | SE_INT_FOV | SE_INT_TXEMP
|
s->im = SE_INT_PHY | SE_INT_MD | SE_INT_RXER | SE_INT_FOV | SE_INT_TXEMP
|
||||||
| SE_INT_TXER | SE_INT_RX;
|
| SE_INT_TXER | SE_INT_RX;
|
||||||
s->thr = 0x3f;
|
s->thr = 0x3f;
|
||||||
s->tx_frame_len = -1;
|
s->tx_fifo_len = 0;
|
||||||
}
|
|
||||||
|
|
||||||
static void stellaris_enet_save(QEMUFile *f, void *opaque)
|
|
||||||
{
|
|
||||||
stellaris_enet_state *s = (stellaris_enet_state *)opaque;
|
|
||||||
int i;
|
|
||||||
|
|
||||||
qemu_put_be32(f, s->ris);
|
|
||||||
qemu_put_be32(f, s->im);
|
|
||||||
qemu_put_be32(f, s->rctl);
|
|
||||||
qemu_put_be32(f, s->tctl);
|
|
||||||
qemu_put_be32(f, s->thr);
|
|
||||||
qemu_put_be32(f, s->mctl);
|
|
||||||
qemu_put_be32(f, s->mdv);
|
|
||||||
qemu_put_be32(f, s->mtxd);
|
|
||||||
qemu_put_be32(f, s->mrxd);
|
|
||||||
qemu_put_be32(f, s->np);
|
|
||||||
qemu_put_be32(f, s->tx_frame_len);
|
|
||||||
qemu_put_be32(f, s->tx_fifo_len);
|
|
||||||
qemu_put_buffer(f, s->tx_fifo, sizeof(s->tx_fifo));
|
|
||||||
for (i = 0; i < 31; i++) {
|
|
||||||
qemu_put_be32(f, s->rx[i].len);
|
|
||||||
qemu_put_buffer(f, s->rx[i].data, sizeof(s->rx[i].data));
|
|
||||||
|
|
||||||
}
|
|
||||||
qemu_put_be32(f, s->next_packet);
|
|
||||||
qemu_put_be32(f, s->rx_fifo - s->rx[s->next_packet].data);
|
|
||||||
qemu_put_be32(f, s->rx_fifo_len);
|
|
||||||
}
|
|
||||||
|
|
||||||
static int stellaris_enet_load(QEMUFile *f, void *opaque, int version_id)
|
|
||||||
{
|
|
||||||
stellaris_enet_state *s = (stellaris_enet_state *)opaque;
|
|
||||||
int i;
|
|
||||||
|
|
||||||
if (version_id != 1)
|
|
||||||
return -EINVAL;
|
|
||||||
|
|
||||||
s->ris = qemu_get_be32(f);
|
|
||||||
s->im = qemu_get_be32(f);
|
|
||||||
s->rctl = qemu_get_be32(f);
|
|
||||||
s->tctl = qemu_get_be32(f);
|
|
||||||
s->thr = qemu_get_be32(f);
|
|
||||||
s->mctl = qemu_get_be32(f);
|
|
||||||
s->mdv = qemu_get_be32(f);
|
|
||||||
s->mtxd = qemu_get_be32(f);
|
|
||||||
s->mrxd = qemu_get_be32(f);
|
|
||||||
s->np = qemu_get_be32(f);
|
|
||||||
s->tx_frame_len = qemu_get_be32(f);
|
|
||||||
s->tx_fifo_len = qemu_get_be32(f);
|
|
||||||
qemu_get_buffer(f, s->tx_fifo, sizeof(s->tx_fifo));
|
|
||||||
for (i = 0; i < 31; i++) {
|
|
||||||
s->rx[i].len = qemu_get_be32(f);
|
|
||||||
qemu_get_buffer(f, s->rx[i].data, sizeof(s->rx[i].data));
|
|
||||||
|
|
||||||
}
|
|
||||||
s->next_packet = qemu_get_be32(f);
|
|
||||||
s->rx_fifo = s->rx[s->next_packet].data + qemu_get_be32(f);
|
|
||||||
s->rx_fifo_len = qemu_get_be32(f);
|
|
||||||
|
|
||||||
return 0;
|
|
||||||
}
|
}
|
||||||
|
|
||||||
static void stellaris_enet_cleanup(NetClientState *nc)
|
static void stellaris_enet_cleanup(NetClientState *nc)
|
||||||
|
@ -419,8 +482,6 @@ static int stellaris_enet_init(SysBusDevice *sbd)
|
||||||
qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a);
|
qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a);
|
||||||
|
|
||||||
stellaris_enet_reset(s);
|
stellaris_enet_reset(s);
|
||||||
register_savevm(dev, "stellaris_enet", -1, 1,
|
|
||||||
stellaris_enet_save, stellaris_enet_load, s);
|
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -428,8 +489,6 @@ static void stellaris_enet_unrealize(DeviceState *dev, Error **errp)
|
||||||
{
|
{
|
||||||
stellaris_enet_state *s = STELLARIS_ENET(dev);
|
stellaris_enet_state *s = STELLARIS_ENET(dev);
|
||||||
|
|
||||||
unregister_savevm(DEVICE(s), "stellaris_enet", s);
|
|
||||||
|
|
||||||
memory_region_destroy(&s->mmio);
|
memory_region_destroy(&s->mmio);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -446,6 +505,7 @@ static void stellaris_enet_class_init(ObjectClass *klass, void *data)
|
||||||
k->init = stellaris_enet_init;
|
k->init = stellaris_enet_init;
|
||||||
dc->unrealize = stellaris_enet_unrealize;
|
dc->unrealize = stellaris_enet_unrealize;
|
||||||
dc->props = stellaris_enet_properties;
|
dc->props = stellaris_enet_properties;
|
||||||
|
dc->vmsd = &vmstate_stellaris_enet;
|
||||||
}
|
}
|
||||||
|
|
||||||
static const TypeInfo stellaris_enet_info = {
|
static const TypeInfo stellaris_enet_info = {
|
||||||
|
|
|
@ -257,7 +257,6 @@ static const VMStateDescription vmstate_pl022 = {
|
||||||
.name = "pl022_ssp",
|
.name = "pl022_ssp",
|
||||||
.version_id = 1,
|
.version_id = 1,
|
||||||
.minimum_version_id = 1,
|
.minimum_version_id = 1,
|
||||||
.minimum_version_id_old = 1,
|
|
||||||
.post_load = pl022_post_load,
|
.post_load = pl022_post_load,
|
||||||
.fields = (VMStateField[]) {
|
.fields = (VMStateField[]) {
|
||||||
VMSTATE_UINT32(cr0, PL022State),
|
VMSTATE_UINT32(cr0, PL022State),
|
||||||
|
|
|
@ -126,7 +126,6 @@ const VMStateDescription vmstate_ssi_slave = {
|
||||||
.name = "SSISlave",
|
.name = "SSISlave",
|
||||||
.version_id = 1,
|
.version_id = 1,
|
||||||
.minimum_version_id = 1,
|
.minimum_version_id = 1,
|
||||||
.minimum_version_id_old = 1,
|
|
||||||
.fields = (VMStateField[]) {
|
.fields = (VMStateField[]) {
|
||||||
VMSTATE_BOOL(cs, SSISlave),
|
VMSTATE_BOOL(cs, SSISlave),
|
||||||
VMSTATE_END_OF_LIST()
|
VMSTATE_END_OF_LIST()
|
||||||
|
|
|
@ -351,7 +351,6 @@ static const VMStateDescription vmstate_xilinx_spi = {
|
||||||
.name = "xilinx_spi",
|
.name = "xilinx_spi",
|
||||||
.version_id = 1,
|
.version_id = 1,
|
||||||
.minimum_version_id = 1,
|
.minimum_version_id = 1,
|
||||||
.minimum_version_id_old = 1,
|
|
||||||
.fields = (VMStateField[]) {
|
.fields = (VMStateField[]) {
|
||||||
VMSTATE_FIFO8(tx_fifo, XilinxSPI),
|
VMSTATE_FIFO8(tx_fifo, XilinxSPI),
|
||||||
VMSTATE_FIFO8(rx_fifo, XilinxSPI),
|
VMSTATE_FIFO8(rx_fifo, XilinxSPI),
|
||||||
|
|
|
@ -704,7 +704,6 @@ static const VMStateDescription vmstate_xilinx_spips = {
|
||||||
.name = "xilinx_spips",
|
.name = "xilinx_spips",
|
||||||
.version_id = 2,
|
.version_id = 2,
|
||||||
.minimum_version_id = 2,
|
.minimum_version_id = 2,
|
||||||
.minimum_version_id_old = 2,
|
|
||||||
.post_load = xilinx_spips_post_load,
|
.post_load = xilinx_spips_post_load,
|
||||||
.fields = (VMStateField[]) {
|
.fields = (VMStateField[]) {
|
||||||
VMSTATE_FIFO8(tx_fifo, XilinxSPIPS),
|
VMSTATE_FIFO8(tx_fifo, XilinxSPIPS),
|
||||||
|
|
|
@ -190,7 +190,6 @@ static const VMStateDescription vmstate_a10_pit = {
|
||||||
.name = "a10.pit",
|
.name = "a10.pit",
|
||||||
.version_id = 1,
|
.version_id = 1,
|
||||||
.minimum_version_id = 1,
|
.minimum_version_id = 1,
|
||||||
.minimum_version_id_old = 1,
|
|
||||||
.fields = (VMStateField[]) {
|
.fields = (VMStateField[]) {
|
||||||
VMSTATE_UINT32(irq_enable, AwA10PITState),
|
VMSTATE_UINT32(irq_enable, AwA10PITState),
|
||||||
VMSTATE_UINT32(irq_status, AwA10PITState),
|
VMSTATE_UINT32(irq_status, AwA10PITState),
|
||||||
|
|
|
@ -150,7 +150,6 @@ static const VMStateDescription vmstate_arm_timer = {
|
||||||
.name = "arm_timer",
|
.name = "arm_timer",
|
||||||
.version_id = 1,
|
.version_id = 1,
|
||||||
.minimum_version_id = 1,
|
.minimum_version_id = 1,
|
||||||
.minimum_version_id_old = 1,
|
|
||||||
.fields = (VMStateField[]) {
|
.fields = (VMStateField[]) {
|
||||||
VMSTATE_UINT32(control, arm_timer_state),
|
VMSTATE_UINT32(control, arm_timer_state),
|
||||||
VMSTATE_UINT32(limit, arm_timer_state),
|
VMSTATE_UINT32(limit, arm_timer_state),
|
||||||
|
@ -271,7 +270,6 @@ static const VMStateDescription vmstate_sp804 = {
|
||||||
.name = "sp804",
|
.name = "sp804",
|
||||||
.version_id = 1,
|
.version_id = 1,
|
||||||
.minimum_version_id = 1,
|
.minimum_version_id = 1,
|
||||||
.minimum_version_id_old = 1,
|
|
||||||
.fields = (VMStateField[]) {
|
.fields = (VMStateField[]) {
|
||||||
VMSTATE_INT32_ARRAY(level, SP804State, 2),
|
VMSTATE_INT32_ARRAY(level, SP804State, 2),
|
||||||
VMSTATE_END_OF_LIST()
|
VMSTATE_END_OF_LIST()
|
||||||
|
|
|
@ -443,7 +443,6 @@ static const VMStateDescription vmstate_cadence_timer = {
|
||||||
.name = "cadence_timer",
|
.name = "cadence_timer",
|
||||||
.version_id = 1,
|
.version_id = 1,
|
||||||
.minimum_version_id = 1,
|
.minimum_version_id = 1,
|
||||||
.minimum_version_id_old = 1,
|
|
||||||
.pre_save = cadence_timer_pre_save,
|
.pre_save = cadence_timer_pre_save,
|
||||||
.post_load = cadence_timer_post_load,
|
.post_load = cadence_timer_post_load,
|
||||||
.fields = (VMStateField[]) {
|
.fields = (VMStateField[]) {
|
||||||
|
@ -464,7 +463,6 @@ static const VMStateDescription vmstate_cadence_ttc = {
|
||||||
.name = "cadence_TTC",
|
.name = "cadence_TTC",
|
||||||
.version_id = 1,
|
.version_id = 1,
|
||||||
.minimum_version_id = 1,
|
.minimum_version_id = 1,
|
||||||
.minimum_version_id_old = 1,
|
|
||||||
.fields = (VMStateField[]) {
|
.fields = (VMStateField[]) {
|
||||||
VMSTATE_STRUCT_ARRAY(timer, CadenceTTCState, 3, 0,
|
VMSTATE_STRUCT_ARRAY(timer, CadenceTTCState, 3, 0,
|
||||||
vmstate_cadence_timer,
|
vmstate_cadence_timer,
|
||||||
|
|
|
@ -36,7 +36,6 @@ static const VMStateDescription vmstate_digic_timer = {
|
||||||
.name = "digic.timer",
|
.name = "digic.timer",
|
||||||
.version_id = 1,
|
.version_id = 1,
|
||||||
.minimum_version_id = 1,
|
.minimum_version_id = 1,
|
||||||
.minimum_version_id_old = 1,
|
|
||||||
.fields = (VMStateField[]) {
|
.fields = (VMStateField[]) {
|
||||||
VMSTATE_PTIMER(ptimer, DigicTimerState),
|
VMSTATE_PTIMER(ptimer, DigicTimerState),
|
||||||
VMSTATE_UINT32(control, DigicTimerState),
|
VMSTATE_UINT32(control, DigicTimerState),
|
||||||
|
|
|
@ -40,7 +40,6 @@ static const VMStateDescription vmstate_ds1338 = {
|
||||||
.name = "ds1338",
|
.name = "ds1338",
|
||||||
.version_id = 2,
|
.version_id = 2,
|
||||||
.minimum_version_id = 1,
|
.minimum_version_id = 1,
|
||||||
.minimum_version_id_old = 1,
|
|
||||||
.fields = (VMStateField[]) {
|
.fields = (VMStateField[]) {
|
||||||
VMSTATE_I2C_SLAVE(parent_obj, DS1338State),
|
VMSTATE_I2C_SLAVE(parent_obj, DS1338State),
|
||||||
VMSTATE_INT64(offset, DS1338State),
|
VMSTATE_INT64(offset, DS1338State),
|
||||||
|
|
|
@ -264,7 +264,6 @@ static const VMStateDescription vmstate_tick_timer = {
|
||||||
.name = "exynos4210.mct.tick_timer",
|
.name = "exynos4210.mct.tick_timer",
|
||||||
.version_id = 1,
|
.version_id = 1,
|
||||||
.minimum_version_id = 1,
|
.minimum_version_id = 1,
|
||||||
.minimum_version_id_old = 1,
|
|
||||||
.fields = (VMStateField[]) {
|
.fields = (VMStateField[]) {
|
||||||
VMSTATE_UINT32(cnt_run, struct tick_timer),
|
VMSTATE_UINT32(cnt_run, struct tick_timer),
|
||||||
VMSTATE_UINT32(int_run, struct tick_timer),
|
VMSTATE_UINT32(int_run, struct tick_timer),
|
||||||
|
@ -284,7 +283,6 @@ static const VMStateDescription vmstate_lregs = {
|
||||||
.name = "exynos4210.mct.lregs",
|
.name = "exynos4210.mct.lregs",
|
||||||
.version_id = 1,
|
.version_id = 1,
|
||||||
.minimum_version_id = 1,
|
.minimum_version_id = 1,
|
||||||
.minimum_version_id_old = 1,
|
|
||||||
.fields = (VMStateField[]) {
|
.fields = (VMStateField[]) {
|
||||||
VMSTATE_UINT32_ARRAY(cnt, struct lregs, L_REG_CNT_AMOUNT),
|
VMSTATE_UINT32_ARRAY(cnt, struct lregs, L_REG_CNT_AMOUNT),
|
||||||
VMSTATE_UINT32(tcon, struct lregs),
|
VMSTATE_UINT32(tcon, struct lregs),
|
||||||
|
@ -299,7 +297,6 @@ static const VMStateDescription vmstate_exynos4210_mct_lt = {
|
||||||
.name = "exynos4210.mct.lt",
|
.name = "exynos4210.mct.lt",
|
||||||
.version_id = 1,
|
.version_id = 1,
|
||||||
.minimum_version_id = 1,
|
.minimum_version_id = 1,
|
||||||
.minimum_version_id_old = 1,
|
|
||||||
.fields = (VMStateField[]) {
|
.fields = (VMStateField[]) {
|
||||||
VMSTATE_INT32(id, Exynos4210MCTLT),
|
VMSTATE_INT32(id, Exynos4210MCTLT),
|
||||||
VMSTATE_STRUCT(tick_timer, Exynos4210MCTLT, 0,
|
VMSTATE_STRUCT(tick_timer, Exynos4210MCTLT, 0,
|
||||||
|
@ -317,7 +314,6 @@ static const VMStateDescription vmstate_gregs = {
|
||||||
.name = "exynos4210.mct.lregs",
|
.name = "exynos4210.mct.lregs",
|
||||||
.version_id = 1,
|
.version_id = 1,
|
||||||
.minimum_version_id = 1,
|
.minimum_version_id = 1,
|
||||||
.minimum_version_id_old = 1,
|
|
||||||
.fields = (VMStateField[]) {
|
.fields = (VMStateField[]) {
|
||||||
VMSTATE_UINT64(cnt, struct gregs),
|
VMSTATE_UINT64(cnt, struct gregs),
|
||||||
VMSTATE_UINT32(cnt_wstat, struct gregs),
|
VMSTATE_UINT32(cnt_wstat, struct gregs),
|
||||||
|
@ -336,7 +332,6 @@ static const VMStateDescription vmstate_exynos4210_mct_gt = {
|
||||||
.name = "exynos4210.mct.lt",
|
.name = "exynos4210.mct.lt",
|
||||||
.version_id = 1,
|
.version_id = 1,
|
||||||
.minimum_version_id = 1,
|
.minimum_version_id = 1,
|
||||||
.minimum_version_id_old = 1,
|
|
||||||
.fields = (VMStateField[]) {
|
.fields = (VMStateField[]) {
|
||||||
VMSTATE_STRUCT(reg, Exynos4210MCTGT, 0, vmstate_gregs,
|
VMSTATE_STRUCT(reg, Exynos4210MCTGT, 0, vmstate_gregs,
|
||||||
struct gregs),
|
struct gregs),
|
||||||
|
@ -351,7 +346,6 @@ static const VMStateDescription vmstate_exynos4210_mct_state = {
|
||||||
.name = "exynos4210.mct",
|
.name = "exynos4210.mct",
|
||||||
.version_id = 1,
|
.version_id = 1,
|
||||||
.minimum_version_id = 1,
|
.minimum_version_id = 1,
|
||||||
.minimum_version_id_old = 1,
|
|
||||||
.fields = (VMStateField[]) {
|
.fields = (VMStateField[]) {
|
||||||
VMSTATE_UINT32(reg_mct_cfg, Exynos4210MCTState),
|
VMSTATE_UINT32(reg_mct_cfg, Exynos4210MCTState),
|
||||||
VMSTATE_STRUCT_ARRAY(l_timer, Exynos4210MCTState, 2, 0,
|
VMSTATE_STRUCT_ARRAY(l_timer, Exynos4210MCTState, 2, 0,
|
||||||
|
@ -824,14 +818,14 @@ static void exynos4210_ltick_recalc_count(struct tick_timer *s)
|
||||||
*/
|
*/
|
||||||
|
|
||||||
if (s->last_tcnto) {
|
if (s->last_tcnto) {
|
||||||
to_count = s->last_tcnto * s->last_icnto;
|
to_count = (uint64_t)s->last_tcnto * s->last_icnto;
|
||||||
} else {
|
} else {
|
||||||
to_count = s->last_icnto;
|
to_count = s->last_icnto;
|
||||||
}
|
}
|
||||||
} else {
|
} else {
|
||||||
/* distance is passed, recalculate with tcnto * icnto */
|
/* distance is passed, recalculate with tcnto * icnto */
|
||||||
if (s->icntb) {
|
if (s->icntb) {
|
||||||
s->distance = s->tcntb * s->icntb;
|
s->distance = (uint64_t)s->tcntb * s->icntb;
|
||||||
} else {
|
} else {
|
||||||
s->distance = s->tcntb;
|
s->distance = s->tcntb;
|
||||||
}
|
}
|
||||||
|
|
|
@ -120,7 +120,6 @@ static const VMStateDescription vmstate_exynos4210_pwm = {
|
||||||
.name = "exynos4210.pwm.pwm",
|
.name = "exynos4210.pwm.pwm",
|
||||||
.version_id = 1,
|
.version_id = 1,
|
||||||
.minimum_version_id = 1,
|
.minimum_version_id = 1,
|
||||||
.minimum_version_id_old = 1,
|
|
||||||
.fields = (VMStateField[]) {
|
.fields = (VMStateField[]) {
|
||||||
VMSTATE_UINT32(id, Exynos4210PWM),
|
VMSTATE_UINT32(id, Exynos4210PWM),
|
||||||
VMSTATE_UINT32(freq, Exynos4210PWM),
|
VMSTATE_UINT32(freq, Exynos4210PWM),
|
||||||
|
@ -135,7 +134,6 @@ static const VMStateDescription vmstate_exynos4210_pwm_state = {
|
||||||
.name = "exynos4210.pwm",
|
.name = "exynos4210.pwm",
|
||||||
.version_id = 1,
|
.version_id = 1,
|
||||||
.minimum_version_id = 1,
|
.minimum_version_id = 1,
|
||||||
.minimum_version_id_old = 1,
|
|
||||||
.fields = (VMStateField[]) {
|
.fields = (VMStateField[]) {
|
||||||
VMSTATE_UINT32_ARRAY(reg_tcfg, Exynos4210PWMState, 2),
|
VMSTATE_UINT32_ARRAY(reg_tcfg, Exynos4210PWMState, 2),
|
||||||
VMSTATE_UINT32(reg_tcon, Exynos4210PWMState),
|
VMSTATE_UINT32(reg_tcon, Exynos4210PWMState),
|
||||||
|
|
|
@ -118,7 +118,6 @@ static const VMStateDescription vmstate_exynos4210_rtc_state = {
|
||||||
.name = "exynos4210.rtc",
|
.name = "exynos4210.rtc",
|
||||||
.version_id = 1,
|
.version_id = 1,
|
||||||
.minimum_version_id = 1,
|
.minimum_version_id = 1,
|
||||||
.minimum_version_id_old = 1,
|
|
||||||
.fields = (VMStateField[]) {
|
.fields = (VMStateField[]) {
|
||||||
VMSTATE_UINT32(reg_intp, Exynos4210RTCState),
|
VMSTATE_UINT32(reg_intp, Exynos4210RTCState),
|
||||||
VMSTATE_UINT32(reg_rtccon, Exynos4210RTCState),
|
VMSTATE_UINT32(reg_rtccon, Exynos4210RTCState),
|
||||||
|
|
|
@ -353,7 +353,6 @@ static const VMStateDescription vmstate_imx_timer_epit = {
|
||||||
.name = "imx.epit",
|
.name = "imx.epit",
|
||||||
.version_id = 2,
|
.version_id = 2,
|
||||||
.minimum_version_id = 2,
|
.minimum_version_id = 2,
|
||||||
.minimum_version_id_old = 2,
|
|
||||||
.fields = (VMStateField[]) {
|
.fields = (VMStateField[]) {
|
||||||
VMSTATE_UINT32(cr, IMXEPITState),
|
VMSTATE_UINT32(cr, IMXEPITState),
|
||||||
VMSTATE_UINT32(sr, IMXEPITState),
|
VMSTATE_UINT32(sr, IMXEPITState),
|
||||||
|
|
|
@ -146,7 +146,6 @@ static const VMStateDescription vmstate_imx_timer_gpt = {
|
||||||
.name = "imx.gpt",
|
.name = "imx.gpt",
|
||||||
.version_id = 3,
|
.version_id = 3,
|
||||||
.minimum_version_id = 3,
|
.minimum_version_id = 3,
|
||||||
.minimum_version_id_old = 3,
|
|
||||||
.fields = (VMStateField[]) {
|
.fields = (VMStateField[]) {
|
||||||
VMSTATE_UINT32(cr, IMXGPTState),
|
VMSTATE_UINT32(cr, IMXGPTState),
|
||||||
VMSTATE_UINT32(pr, IMXGPTState),
|
VMSTATE_UINT32(pr, IMXGPTState),
|
||||||
|
|
|
@ -476,7 +476,6 @@ static const VMStateDescription vmstate_pxa2xx_timer0_regs = {
|
||||||
.name = "pxa2xx_timer0",
|
.name = "pxa2xx_timer0",
|
||||||
.version_id = 2,
|
.version_id = 2,
|
||||||
.minimum_version_id = 2,
|
.minimum_version_id = 2,
|
||||||
.minimum_version_id_old = 2,
|
|
||||||
.fields = (VMStateField[]) {
|
.fields = (VMStateField[]) {
|
||||||
VMSTATE_UINT32(value, PXA2xxTimer0),
|
VMSTATE_UINT32(value, PXA2xxTimer0),
|
||||||
VMSTATE_END_OF_LIST(),
|
VMSTATE_END_OF_LIST(),
|
||||||
|
@ -487,7 +486,6 @@ static const VMStateDescription vmstate_pxa2xx_timer4_regs = {
|
||||||
.name = "pxa2xx_timer4",
|
.name = "pxa2xx_timer4",
|
||||||
.version_id = 1,
|
.version_id = 1,
|
||||||
.minimum_version_id = 1,
|
.minimum_version_id = 1,
|
||||||
.minimum_version_id_old = 1,
|
|
||||||
.fields = (VMStateField[]) {
|
.fields = (VMStateField[]) {
|
||||||
VMSTATE_STRUCT(tm, PXA2xxTimer4, 1,
|
VMSTATE_STRUCT(tm, PXA2xxTimer4, 1,
|
||||||
vmstate_pxa2xx_timer0_regs, PXA2xxTimer0),
|
vmstate_pxa2xx_timer0_regs, PXA2xxTimer0),
|
||||||
|
@ -509,7 +507,6 @@ static const VMStateDescription vmstate_pxa2xx_timer_regs = {
|
||||||
.name = "pxa2xx_timer",
|
.name = "pxa2xx_timer",
|
||||||
.version_id = 1,
|
.version_id = 1,
|
||||||
.minimum_version_id = 1,
|
.minimum_version_id = 1,
|
||||||
.minimum_version_id_old = 1,
|
|
||||||
.post_load = pxa25x_timer_post_load,
|
.post_load = pxa25x_timer_post_load,
|
||||||
.fields = (VMStateField[]) {
|
.fields = (VMStateField[]) {
|
||||||
VMSTATE_INT32(clock, PXA2xxTimerInfo),
|
VMSTATE_INT32(clock, PXA2xxTimerInfo),
|
||||||
|
|
|
@ -772,8 +772,7 @@ static const VMStateDescription vmstate_menelaus_tm = {
|
||||||
.name = "menelaus_tm",
|
.name = "menelaus_tm",
|
||||||
.version_id = 0,
|
.version_id = 0,
|
||||||
.minimum_version_id = 0,
|
.minimum_version_id = 0,
|
||||||
.minimum_version_id_old = 0,
|
.fields = (VMStateField[]) {
|
||||||
.fields = (VMStateField []) {
|
|
||||||
VMSTATE_UINT16_HACK(tm_sec, struct tm),
|
VMSTATE_UINT16_HACK(tm_sec, struct tm),
|
||||||
VMSTATE_UINT16_HACK(tm_min, struct tm),
|
VMSTATE_UINT16_HACK(tm_min, struct tm),
|
||||||
VMSTATE_UINT16_HACK(tm_hour, struct tm),
|
VMSTATE_UINT16_HACK(tm_hour, struct tm),
|
||||||
|
@ -811,10 +810,9 @@ static const VMStateDescription vmstate_menelaus = {
|
||||||
.name = "menelaus",
|
.name = "menelaus",
|
||||||
.version_id = 0,
|
.version_id = 0,
|
||||||
.minimum_version_id = 0,
|
.minimum_version_id = 0,
|
||||||
.minimum_version_id_old = 0,
|
|
||||||
.pre_save = menelaus_pre_save,
|
.pre_save = menelaus_pre_save,
|
||||||
.post_load = menelaus_post_load,
|
.post_load = menelaus_post_load,
|
||||||
.fields = (VMStateField []) {
|
.fields = (VMStateField[]) {
|
||||||
VMSTATE_INT32(firstbyte, MenelausState),
|
VMSTATE_INT32(firstbyte, MenelausState),
|
||||||
VMSTATE_UINT8(reg, MenelausState),
|
VMSTATE_UINT8(reg, MenelausState),
|
||||||
VMSTATE_UINT8_ARRAY(vcore, MenelausState, 5),
|
VMSTATE_UINT8_ARRAY(vcore, MenelausState, 5),
|
||||||
|
|
|
@ -2081,6 +2081,13 @@ static void sctlr_write(CPUARMState *env, const ARMCPRegInfo *ri,
|
||||||
{
|
{
|
||||||
ARMCPU *cpu = arm_env_get_cpu(env);
|
ARMCPU *cpu = arm_env_get_cpu(env);
|
||||||
|
|
||||||
|
if (env->cp15.c1_sys == value) {
|
||||||
|
/* Skip the TLB flush if nothing actually changed; Linux likes
|
||||||
|
* to do a lot of pointless SCTLR writes.
|
||||||
|
*/
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
|
||||||
env->cp15.c1_sys = value;
|
env->cp15.c1_sys = value;
|
||||||
/* ??? Lots of these bits are not implemented. */
|
/* ??? Lots of these bits are not implemented. */
|
||||||
/* This may enable/disable the MMU, so do a TLB flush. */
|
/* This may enable/disable the MMU, so do a TLB flush. */
|
||||||
|
|
|
@ -39,7 +39,6 @@ static const VMStateDescription vmstate_vfp = {
|
||||||
.name = "cpu/vfp",
|
.name = "cpu/vfp",
|
||||||
.version_id = 3,
|
.version_id = 3,
|
||||||
.minimum_version_id = 3,
|
.minimum_version_id = 3,
|
||||||
.minimum_version_id_old = 3,
|
|
||||||
.fields = (VMStateField[]) {
|
.fields = (VMStateField[]) {
|
||||||
VMSTATE_FLOAT64_ARRAY(env.vfp.regs, ARMCPU, 64),
|
VMSTATE_FLOAT64_ARRAY(env.vfp.regs, ARMCPU, 64),
|
||||||
/* The xregs array is a little awkward because element 1 (FPSCR)
|
/* The xregs array is a little awkward because element 1 (FPSCR)
|
||||||
|
@ -72,7 +71,6 @@ static const VMStateDescription vmstate_iwmmxt = {
|
||||||
.name = "cpu/iwmmxt",
|
.name = "cpu/iwmmxt",
|
||||||
.version_id = 1,
|
.version_id = 1,
|
||||||
.minimum_version_id = 1,
|
.minimum_version_id = 1,
|
||||||
.minimum_version_id_old = 1,
|
|
||||||
.fields = (VMStateField[]) {
|
.fields = (VMStateField[]) {
|
||||||
VMSTATE_UINT64_ARRAY(env.iwmmxt.regs, ARMCPU, 16),
|
VMSTATE_UINT64_ARRAY(env.iwmmxt.regs, ARMCPU, 16),
|
||||||
VMSTATE_UINT32_ARRAY(env.iwmmxt.cregs, ARMCPU, 16),
|
VMSTATE_UINT32_ARRAY(env.iwmmxt.cregs, ARMCPU, 16),
|
||||||
|
@ -92,7 +90,6 @@ static const VMStateDescription vmstate_m = {
|
||||||
.name = "cpu/m",
|
.name = "cpu/m",
|
||||||
.version_id = 1,
|
.version_id = 1,
|
||||||
.minimum_version_id = 1,
|
.minimum_version_id = 1,
|
||||||
.minimum_version_id_old = 1,
|
|
||||||
.fields = (VMStateField[]) {
|
.fields = (VMStateField[]) {
|
||||||
VMSTATE_UINT32(env.v7m.other_sp, ARMCPU),
|
VMSTATE_UINT32(env.v7m.other_sp, ARMCPU),
|
||||||
VMSTATE_UINT32(env.v7m.vecbase, ARMCPU),
|
VMSTATE_UINT32(env.v7m.vecbase, ARMCPU),
|
||||||
|
@ -116,7 +113,6 @@ static const VMStateDescription vmstate_thumb2ee = {
|
||||||
.name = "cpu/thumb2ee",
|
.name = "cpu/thumb2ee",
|
||||||
.version_id = 1,
|
.version_id = 1,
|
||||||
.minimum_version_id = 1,
|
.minimum_version_id = 1,
|
||||||
.minimum_version_id_old = 1,
|
|
||||||
.fields = (VMStateField[]) {
|
.fields = (VMStateField[]) {
|
||||||
VMSTATE_UINT32(env.teecr, ARMCPU),
|
VMSTATE_UINT32(env.teecr, ARMCPU),
|
||||||
VMSTATE_UINT32(env.teehbr, ARMCPU),
|
VMSTATE_UINT32(env.teehbr, ARMCPU),
|
||||||
|
@ -224,7 +220,6 @@ const VMStateDescription vmstate_arm_cpu = {
|
||||||
.name = "cpu",
|
.name = "cpu",
|
||||||
.version_id = 17,
|
.version_id = 17,
|
||||||
.minimum_version_id = 17,
|
.minimum_version_id = 17,
|
||||||
.minimum_version_id_old = 17,
|
|
||||||
.pre_save = cpu_pre_save,
|
.pre_save = cpu_pre_save,
|
||||||
.post_load = cpu_post_load,
|
.post_load = cpu_post_load,
|
||||||
.fields = (VMStateField[]) {
|
.fields = (VMStateField[]) {
|
||||||
|
|
|
@ -116,7 +116,6 @@ const VMStateDescription vmstate_fifo8 = {
|
||||||
.name = "Fifo8",
|
.name = "Fifo8",
|
||||||
.version_id = 1,
|
.version_id = 1,
|
||||||
.minimum_version_id = 1,
|
.minimum_version_id = 1,
|
||||||
.minimum_version_id_old = 1,
|
|
||||||
.fields = (VMStateField[]) {
|
.fields = (VMStateField[]) {
|
||||||
VMSTATE_VBUFFER_UINT32(data, Fifo8, 1, NULL, 0, capacity),
|
VMSTATE_VBUFFER_UINT32(data, Fifo8, 1, NULL, 0, capacity),
|
||||||
VMSTATE_UINT32(head, Fifo8),
|
VMSTATE_UINT32(head, Fifo8),
|
||||||
|
|
Loading…
Reference in a new issue