Remove ctx->env ptr, add TriCore gdb stub
-----BEGIN PGP SIGNATURE----- iQJTBAABCgA9FiEEbmNqfoPy3Qz6bm43CtLGOWtpyhQFAl7VGXsfHGtiYXN0aWFu QG1haWwudW5pLXBhZGVyYm9ybi5kZQAKCRAK0sY5a2nKFHLSD/0dg9o3F24vm8PF oII8nPZO0S4tDLlTuqWsWtsOLRZ/AEdHHfwQTr8NRhjlInt1/ij13KEt+riEhQQN Ul6qUc3eKjbzo0sZ6Sd83ne/5qTicSrxU8EpJqopm9LxYMpKSgymJNT1SEJo5hcK XUC+hUxi9eFdQ3grKJm0y9uWTGAS9kbZtHqHPLwYQqGbelDRX3N0Tr2WeTX7Bq1B gK43ZhZYZlyQGw5ogiQGNjhFWD1/+Wb64FsgeKSn4lzqXQABckljFabDd2xDPdeF lSs4/O3URpnJuixaqkUM1bVZyXiJf2AFwBvLYw+HM/eouq/6pfzYbqLeppwgkZMW BqOu6232icidI20H19pv1P7fzCXrIkA/Rz99bLKw+erLfB9wJiOxV7Xr/4clpGog hODjlERnToewUH3DWw5k4Fo2scAABlfAqaX1WAjfbCh3rgebgfcqezZEmIbkZVOk GsS6fWdo0xG+lvdrVHe9aDji/iPBvwPCbHPHT77DwbJPaDZ96D3q9r6fve1hrlpG /NfC9+C+Qh9Gl1JqAiiIGlBLgUFGr68GyBD3iL3VF0uq57C82AKtcYqD/aqjlGnN Z5MbKlYMUiSL6euDwDkq5Tum3DXD1x5C32LDxl99R+KSjSXOsbjBfcS18tne5N/G yEIkgNdfY+4IzlPxlevYUOb21c2leg== =Xjoi -----END PGP SIGNATURE----- Merge remote-tracking branch 'remotes/bkoppelmann2/tags/pull-tricore-20200601' into staging Remove ctx->env ptr, add TriCore gdb stub # gpg: Signature made Mon 01 Jun 2020 16:06:35 BST # gpg: using RSA key 6E636A7E83F2DD0CFA6E6E370AD2C6396B69CA14 # gpg: issuer "kbastian@mail.uni-paderborn.de" # gpg: Good signature from "Bastian Koppelmann <kbastian@mail.uni-paderborn.de>" [full] # Primary key fingerprint: 6E63 6A7E 83F2 DD0C FA6E 6E37 0AD2 C639 6B69 CA14 * remotes/bkoppelmann2/tags/pull-tricore-20200601: target/tricore: Implement gdbstub target/tricore: Implement tricore_cpu_get_phys_page_debug target/tricore: Raise EXCP_DEBUG in gen_goto_tb() for singlestep target/tricore: Move translate feature check to ctx target/tricore: Don't save pc in generate_qemu_excp Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
commit
6bb228190e
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@ -1 +1 @@
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obj-y += translate.o helper.o cpu.o op_helper.o fpu_helper.o
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obj-y += translate.o helper.o cpu.o op_helper.o fpu_helper.o gdbstub.o
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@ -23,19 +23,16 @@
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#include "exec/exec-all.h"
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#include "qemu/error-report.h"
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static hwaddr tricore_cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr,
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MemTxAttrs *attrs)
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{
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error_report("function cpu_get_phys_page_attrs_debug not "
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"implemented, aborting");
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return -1;
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}
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static inline void set_feature(CPUTriCoreState *env, int feature)
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{
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env->features |= 1ULL << feature;
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}
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static gchar *tricore_gdb_arch_name(CPUState *cs)
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{
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return g_strdup("tricore");
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}
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static void tricore_cpu_set_pc(CPUState *cs, vaddr value)
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{
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TriCoreCPU *cpu = TRICORE_CPU(cs);
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@ -158,10 +155,15 @@ static void tricore_cpu_class_init(ObjectClass *c, void *data)
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cc->class_by_name = tricore_cpu_class_by_name;
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cc->has_work = tricore_cpu_has_work;
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cc->gdb_read_register = tricore_cpu_gdb_read_register;
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cc->gdb_write_register = tricore_cpu_gdb_write_register;
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cc->gdb_num_core_regs = 44;
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cc->gdb_arch_name = tricore_gdb_arch_name;
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cc->dump_state = tricore_cpu_dump_state;
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cc->set_pc = tricore_cpu_set_pc;
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cc->synchronize_from_tb = tricore_cpu_synchronize_from_tb;
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cc->get_phys_page_attrs_debug = tricore_cpu_get_phys_page_attrs_debug;
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cc->get_phys_page_debug = tricore_cpu_get_phys_page_debug;
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cc->tcg_initialize = tricore_tcg_init;
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cc->tlb_fill = tricore_cpu_tlb_fill;
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}
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@ -353,6 +353,8 @@ enum {
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uint32_t psw_read(CPUTriCoreState *env);
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void psw_write(CPUTriCoreState *env, uint32_t val);
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int tricore_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n);
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int tricore_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n);
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void fpu_set_state(CPUTriCoreState *env);
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139
target/tricore/gdbstub.c
Normal file
139
target/tricore/gdbstub.c
Normal file
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@ -0,0 +1,139 @@
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/*
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* TriCore gdb server stub
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*
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* Copyright (c) 2019 Bastian Koppelmann, Paderborn University
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "qemu-common.h"
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#include "exec/gdbstub.h"
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#define LCX_REGNUM 32
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#define FCX_REGNUM 33
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#define PCXI_REGNUM 34
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#define TRICORE_PSW_REGNUM 35
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#define TRICORE_PC_REGNUM 36
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#define ICR_REGNUM 37
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#define ISP_REGNUM 38
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#define BTV_REGNUM 39
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#define BIV_REGNUM 40
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#define SYSCON_REGNUM 41
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#define PMUCON0_REGNUM 42
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#define DMUCON_REGNUM 43
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static uint32_t tricore_cpu_gdb_read_csfr(CPUTriCoreState *env, int n)
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{
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switch (n) {
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case LCX_REGNUM:
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return env->LCX;
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case FCX_REGNUM:
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return env->FCX;
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case PCXI_REGNUM:
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return env->PCXI;
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case TRICORE_PSW_REGNUM:
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return psw_read(env);
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case TRICORE_PC_REGNUM:
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return env->PC;
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case ICR_REGNUM:
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return env->ICR;
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case ISP_REGNUM:
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return env->ISP;
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case BTV_REGNUM:
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return env->BTV;
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case BIV_REGNUM:
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return env->BIV;
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case SYSCON_REGNUM:
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return env->SYSCON;
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case PMUCON0_REGNUM:
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return 0; /* PMUCON0 */
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case DMUCON_REGNUM:
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return 0; /* DMUCON0 */
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default:
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return 0;
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}
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}
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static void tricore_cpu_gdb_write_csfr(CPUTriCoreState *env, int n,
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uint32_t val)
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{
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switch (n) {
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case LCX_REGNUM:
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env->LCX = val;
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break;
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case FCX_REGNUM:
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env->FCX = val;
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break;
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case PCXI_REGNUM:
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env->PCXI = val;
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break;
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case TRICORE_PSW_REGNUM:
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psw_write(env, val);
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break;
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case TRICORE_PC_REGNUM:
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env->PC = val;
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break;
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case ICR_REGNUM:
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env->ICR = val;
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break;
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case ISP_REGNUM:
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env->ISP = val;
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break;
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case BTV_REGNUM:
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env->BTV = val;
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break;
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case BIV_REGNUM:
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env->BIV = val;
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break;
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case SYSCON_REGNUM:
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env->SYSCON = val;
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break;
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}
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}
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int tricore_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
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{
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TriCoreCPU *cpu = TRICORE_CPU(cs);
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CPUTriCoreState *env = &cpu->env;
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if (n < 16) { /* data registers */
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return gdb_get_reg32(mem_buf, env->gpr_d[n]);
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} else if (n < 32) { /* address registers */
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return gdb_get_reg32(mem_buf, env->gpr_a[n - 16]);
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} else { /* csfr */
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return gdb_get_reg32(mem_buf, tricore_cpu_gdb_read_csfr(env, n));
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}
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return 0;
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}
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int tricore_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
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{
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TriCoreCPU *cpu = TRICORE_CPU(cs);
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CPUTriCoreState *env = &cpu->env;
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uint32_t tmp;
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tmp = ldl_p(mem_buf);
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if (n < 16) { /* data registers */
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env->gpr_d[n] = tmp;
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} else if (n < 32) { /* address registers */
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env->gpr_d[n - 16] = tmp;
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} else {
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tricore_cpu_gdb_write_csfr(env, n, tmp);
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}
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return 4;
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}
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@ -42,6 +42,19 @@ static int get_physical_address(CPUTriCoreState *env, hwaddr *physical,
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return ret;
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}
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hwaddr tricore_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
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{
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TriCoreCPU *cpu = TRICORE_CPU(cs);
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hwaddr phys_addr;
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int prot;
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int mmu_idx = cpu_mmu_index(&cpu->env, false);
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if (get_physical_address(&cpu->env, &phys_addr, &prot, addr, 0, mmu_idx)) {
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return -1;
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}
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return phys_addr;
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}
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#endif
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/* TODO: Add exeption support*/
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@ -66,14 +66,19 @@ static const char *regnames_d[] = {
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typedef struct DisasContext {
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DisasContextBase base;
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CPUTriCoreState *env;
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target_ulong pc_succ_insn;
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uint32_t opcode;
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/* Routine used to access memory */
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int mem_idx;
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uint32_t hflags, saved_hflags;
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uint64_t features;
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} DisasContext;
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static int has_feature(DisasContext *ctx, int feature)
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{
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return (ctx->features & (1ULL << feature)) != 0;
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}
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enum {
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MODE_LL = 0,
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MODE_LU = 1,
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@ -370,7 +375,7 @@ static void gen_swapmsk(DisasContext *ctx, int reg, TCGv ea)
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These makros also specify in which ISA version the csfr was introduced. */
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#define R(ADDRESS, REG, FEATURE) \
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case ADDRESS: \
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if (tricore_feature(ctx->env, FEATURE)) { \
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if (has_feature(ctx, FEATURE)) { \
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tcg_gen_ld_tl(ret, cpu_env, offsetof(CPUTriCoreState, REG)); \
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} \
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break;
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@ -395,7 +400,7 @@ static inline void gen_mfcr(DisasContext *ctx, TCGv ret, int32_t offset)
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since no execption occurs */
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#define A(ADDRESS, REG, FEATURE) R(ADDRESS, REG, FEATURE) \
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case ADDRESS: \
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if (tricore_feature(ctx->env, FEATURE)) { \
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if (has_feature(ctx, FEATURE)) { \
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tcg_gen_st_tl(r1, cpu_env, offsetof(CPUTriCoreState, REG)); \
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} \
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break;
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@ -3158,7 +3163,7 @@ gen_dvinit_b(DisasContext *ctx, TCGv rl, TCGv rh, TCGv r1, TCGv r2)
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{
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TCGv_i64 ret = tcg_temp_new_i64();
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if (!tricore_feature(ctx->env, TRICORE_FEATURE_131)) {
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if (!has_feature(ctx, TRICORE_FEATURE_131)) {
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gen_helper_dvinit_b_13(ret, cpu_env, r1, r2);
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} else {
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gen_helper_dvinit_b_131(ret, cpu_env, r1, r2);
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@ -3173,7 +3178,7 @@ gen_dvinit_h(DisasContext *ctx, TCGv rl, TCGv rh, TCGv r1, TCGv r2)
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{
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TCGv_i64 ret = tcg_temp_new_i64();
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if (!tricore_feature(ctx->env, TRICORE_FEATURE_131)) {
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if (!has_feature(ctx, TRICORE_FEATURE_131)) {
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gen_helper_dvinit_h_13(ret, cpu_env, r1, r2);
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} else {
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gen_helper_dvinit_h_131(ret, cpu_env, r1, r2);
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@ -3233,6 +3238,14 @@ static inline bool use_goto_tb(DisasContext *ctx, target_ulong dest)
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#endif
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}
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static void generate_qemu_excp(DisasContext *ctx, int excp)
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{
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TCGv_i32 tmp = tcg_const_i32(excp);
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gen_helper_qemu_excp(cpu_env, tmp);
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ctx->base.is_jmp = DISAS_NORETURN;
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tcg_temp_free(tmp);
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}
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static inline void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
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{
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if (use_goto_tb(ctx, dest)) {
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@ -3242,7 +3255,7 @@ static inline void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
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} else {
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gen_save_pc(dest);
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if (ctx->base.singlestep_enabled) {
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/* raise exception debug */
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generate_qemu_excp(ctx, EXCP_DEBUG);
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}
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tcg_gen_exit_tb(NULL, 0);
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}
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@ -3261,15 +3274,6 @@ static void generate_trap(DisasContext *ctx, int class, int tin)
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tcg_temp_free(tintemp);
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}
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static void generate_qemu_excp(DisasContext *ctx, int excp)
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{
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TCGv_i32 tmp = tcg_const_i32(excp);
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gen_save_pc(ctx->base.pc_next);
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gen_helper_qemu_excp(cpu_env, tmp);
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ctx->base.is_jmp = DISAS_NORETURN;
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tcg_temp_free(tmp);
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}
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static inline void gen_branch_cond(DisasContext *ctx, TCGCond cond, TCGv r1,
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TCGv r2, int16_t address)
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{
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|
@ -3656,7 +3660,7 @@ static void decode_src_opc(DisasContext *ctx, int op1)
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tcg_gen_movi_tl(cpu_gpr_a[r1], const4);
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break;
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case OPC1_16_SRC_MOV_E:
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if (tricore_feature(ctx->env, TRICORE_FEATURE_16)) {
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if (has_feature(ctx, TRICORE_FEATURE_16)) {
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tcg_gen_movi_tl(cpu_gpr_d[r1], const4);
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tcg_gen_sari_tl(cpu_gpr_d[r1+1], cpu_gpr_d[r1], 31);
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} else {
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|
@ -4107,7 +4111,7 @@ static void decode_16Bit_opc(DisasContext *ctx)
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break;
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case OPC1_16_SBC_JEQ2:
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case OPC1_16_SBC_JNE2:
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if (tricore_feature(ctx->env, TRICORE_FEATURE_16)) {
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if (has_feature(ctx, TRICORE_FEATURE_16)) {
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address = MASK_OP_SBC_DISP4(ctx->opcode);
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const16 = MASK_OP_SBC_CONST4_SEXT(ctx->opcode);
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gen_compute_branch(ctx, op1, 0, 0, const16, address);
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|
@ -4125,7 +4129,7 @@ static void decode_16Bit_opc(DisasContext *ctx)
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/* SBR-format */
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case OPC1_16_SBR_JEQ2:
|
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case OPC1_16_SBR_JNE2:
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if (tricore_feature(ctx->env, TRICORE_FEATURE_16)) {
|
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if (has_feature(ctx, TRICORE_FEATURE_16)) {
|
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r1 = MASK_OP_SBR_S2(ctx->opcode);
|
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address = MASK_OP_SBR_DISP4(ctx->opcode);
|
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gen_compute_branch(ctx, op1, r1, 0, 0, address);
|
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|
@ -4705,13 +4709,13 @@ static void decode_bo_addrmode_post_pre_base(DisasContext *ctx)
|
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break;
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case OPC2_32_BO_CACHEI_WI_SHORTOFF:
|
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case OPC2_32_BO_CACHEI_W_SHORTOFF:
|
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if (!tricore_feature(ctx->env, TRICORE_FEATURE_131)) {
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if (!has_feature(ctx, TRICORE_FEATURE_131)) {
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generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
|
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}
|
||||
break;
|
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case OPC2_32_BO_CACHEI_W_POSTINC:
|
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case OPC2_32_BO_CACHEI_WI_POSTINC:
|
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if (tricore_feature(ctx->env, TRICORE_FEATURE_131)) {
|
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if (has_feature(ctx, TRICORE_FEATURE_131)) {
|
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tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
|
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} else {
|
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generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
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|
@ -4719,7 +4723,7 @@ static void decode_bo_addrmode_post_pre_base(DisasContext *ctx)
|
|||
break;
|
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case OPC2_32_BO_CACHEI_W_PREINC:
|
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case OPC2_32_BO_CACHEI_WI_PREINC:
|
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if (tricore_feature(ctx->env, TRICORE_FEATURE_131)) {
|
||||
if (has_feature(ctx, TRICORE_FEATURE_131)) {
|
||||
tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
|
||||
} else {
|
||||
generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
|
||||
|
@ -5373,7 +5377,7 @@ static void decode_bol_opc(DisasContext *ctx, int32_t op1)
|
|||
tcg_gen_addi_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], address);
|
||||
break;
|
||||
case OPC1_32_BOL_ST_A_LONGOFF:
|
||||
if (tricore_feature(ctx->env, TRICORE_FEATURE_16)) {
|
||||
if (has_feature(ctx, TRICORE_FEATURE_16)) {
|
||||
gen_offset_st(ctx, cpu_gpr_a[r1], cpu_gpr_a[r2], address, MO_LEUL);
|
||||
} else {
|
||||
generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
|
||||
|
@ -5383,42 +5387,42 @@ static void decode_bol_opc(DisasContext *ctx, int32_t op1)
|
|||
gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_LEUL);
|
||||
break;
|
||||
case OPC1_32_BOL_LD_B_LONGOFF:
|
||||
if (tricore_feature(ctx->env, TRICORE_FEATURE_16)) {
|
||||
if (has_feature(ctx, TRICORE_FEATURE_16)) {
|
||||
gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_SB);
|
||||
} else {
|
||||
generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
|
||||
}
|
||||
break;
|
||||
case OPC1_32_BOL_LD_BU_LONGOFF:
|
||||
if (tricore_feature(ctx->env, TRICORE_FEATURE_16)) {
|
||||
if (has_feature(ctx, TRICORE_FEATURE_16)) {
|
||||
gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_UB);
|
||||
} else {
|
||||
generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
|
||||
}
|
||||
break;
|
||||
case OPC1_32_BOL_LD_H_LONGOFF:
|
||||
if (tricore_feature(ctx->env, TRICORE_FEATURE_16)) {
|
||||
if (has_feature(ctx, TRICORE_FEATURE_16)) {
|
||||
gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_LESW);
|
||||
} else {
|
||||
generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
|
||||
}
|
||||
break;
|
||||
case OPC1_32_BOL_LD_HU_LONGOFF:
|
||||
if (tricore_feature(ctx->env, TRICORE_FEATURE_16)) {
|
||||
if (has_feature(ctx, TRICORE_FEATURE_16)) {
|
||||
gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_LEUW);
|
||||
} else {
|
||||
generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
|
||||
}
|
||||
break;
|
||||
case OPC1_32_BOL_ST_B_LONGOFF:
|
||||
if (tricore_feature(ctx->env, TRICORE_FEATURE_16)) {
|
||||
if (has_feature(ctx, TRICORE_FEATURE_16)) {
|
||||
gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_SB);
|
||||
} else {
|
||||
generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
|
||||
}
|
||||
break;
|
||||
case OPC1_32_BOL_ST_H_LONGOFF:
|
||||
if (tricore_feature(ctx->env, TRICORE_FEATURE_16)) {
|
||||
if (has_feature(ctx, TRICORE_FEATURE_16)) {
|
||||
gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_LESW);
|
||||
} else {
|
||||
generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
|
||||
|
@ -6023,7 +6027,7 @@ static void decode_rlc_opc(DisasContext *ctx,
|
|||
tcg_gen_movi_tl(cpu_gpr_d[r2], const16);
|
||||
break;
|
||||
case OPC1_32_RLC_MOV_64:
|
||||
if (tricore_feature(ctx->env, TRICORE_FEATURE_16)) {
|
||||
if (has_feature(ctx, TRICORE_FEATURE_16)) {
|
||||
CHECK_REG_PAIR(r2);
|
||||
tcg_gen_movi_tl(cpu_gpr_d[r2], const16);
|
||||
tcg_gen_movi_tl(cpu_gpr_d[r2+1], const16 >> 15);
|
||||
|
@ -6249,7 +6253,7 @@ static void decode_rr_accumulator(DisasContext *ctx)
|
|||
tcg_gen_mov_tl(cpu_gpr_d[r3], cpu_gpr_d[r2]);
|
||||
break;
|
||||
case OPC2_32_RR_MOV_64:
|
||||
if (tricore_feature(ctx->env, TRICORE_FEATURE_16)) {
|
||||
if (has_feature(ctx, TRICORE_FEATURE_16)) {
|
||||
temp = tcg_temp_new();
|
||||
|
||||
CHECK_REG_PAIR(r3);
|
||||
|
@ -6263,7 +6267,7 @@ static void decode_rr_accumulator(DisasContext *ctx)
|
|||
}
|
||||
break;
|
||||
case OPC2_32_RR_MOVS_64:
|
||||
if (tricore_feature(ctx->env, TRICORE_FEATURE_16)) {
|
||||
if (has_feature(ctx, TRICORE_FEATURE_16)) {
|
||||
CHECK_REG_PAIR(r3);
|
||||
tcg_gen_mov_tl(cpu_gpr_d[r3], cpu_gpr_d[r2]);
|
||||
tcg_gen_sari_tl(cpu_gpr_d[r3 + 1], cpu_gpr_d[r2], 31);
|
||||
|
@ -6603,7 +6607,7 @@ static void decode_rr_divide(DisasContext *ctx)
|
|||
tcg_gen_shri_tl(temp3, cpu_gpr_d[r1], 8);
|
||||
/* reset av */
|
||||
tcg_gen_movi_tl(cpu_PSW_AV, 0);
|
||||
if (!tricore_feature(ctx->env, TRICORE_FEATURE_131)) {
|
||||
if (!has_feature(ctx, TRICORE_FEATURE_131)) {
|
||||
/* overflow = (abs(D[r3+1]) >= abs(D[r2])) */
|
||||
tcg_gen_abs_tl(temp, temp3);
|
||||
tcg_gen_abs_tl(temp2, cpu_gpr_d[r2]);
|
||||
|
@ -6636,7 +6640,7 @@ static void decode_rr_divide(DisasContext *ctx)
|
|||
tcg_gen_shri_tl(temp3, cpu_gpr_d[r1], 16);
|
||||
/* reset av */
|
||||
tcg_gen_movi_tl(cpu_PSW_AV, 0);
|
||||
if (!tricore_feature(ctx->env, TRICORE_FEATURE_131)) {
|
||||
if (!has_feature(ctx, TRICORE_FEATURE_131)) {
|
||||
/* overflow = (abs(D[r3+1]) >= abs(D[r2])) */
|
||||
tcg_gen_abs_tl(temp, temp3);
|
||||
tcg_gen_abs_tl(temp2, cpu_gpr_d[r2]);
|
||||
|
@ -6699,14 +6703,14 @@ static void decode_rr_divide(DisasContext *ctx)
|
|||
gen_unpack(cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1]);
|
||||
break;
|
||||
case OPC2_32_RR_CRC32:
|
||||
if (tricore_feature(ctx->env, TRICORE_FEATURE_161)) {
|
||||
if (has_feature(ctx, TRICORE_FEATURE_161)) {
|
||||
gen_helper_crc32(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
|
||||
} else {
|
||||
generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
|
||||
}
|
||||
break;
|
||||
case OPC2_32_RR_DIV:
|
||||
if (tricore_feature(ctx->env, TRICORE_FEATURE_16)) {
|
||||
if (has_feature(ctx, TRICORE_FEATURE_16)) {
|
||||
GEN_HELPER_RR(divide, cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1],
|
||||
cpu_gpr_d[r2]);
|
||||
} else {
|
||||
|
@ -6714,7 +6718,7 @@ static void decode_rr_divide(DisasContext *ctx)
|
|||
}
|
||||
break;
|
||||
case OPC2_32_RR_DIV_U:
|
||||
if (tricore_feature(ctx->env, TRICORE_FEATURE_16)) {
|
||||
if (has_feature(ctx, TRICORE_FEATURE_16)) {
|
||||
GEN_HELPER_RR(divide_u, cpu_gpr_d[r3], cpu_gpr_d[r3+1],
|
||||
cpu_gpr_d[r1], cpu_gpr_d[r2]);
|
||||
} else {
|
||||
|
@ -8412,7 +8416,7 @@ static void decode_sys_interrupts(DisasContext *ctx)
|
|||
gen_helper_svlcx(cpu_env);
|
||||
break;
|
||||
case OPC2_32_SYS_RESTORE:
|
||||
if (tricore_feature(ctx->env, TRICORE_FEATURE_16)) {
|
||||
if (has_feature(ctx, TRICORE_FEATURE_16)) {
|
||||
if ((ctx->hflags & TRICORE_HFLAG_KUU) == TRICORE_HFLAG_SM ||
|
||||
(ctx->hflags & TRICORE_HFLAG_KUU) == TRICORE_HFLAG_UM1) {
|
||||
tcg_gen_deposit_tl(cpu_ICR, cpu_ICR, cpu_gpr_d[r1], 8, 1);
|
||||
|
@ -8793,6 +8797,7 @@ static void tricore_tr_init_disas_context(DisasContextBase *dcbase,
|
|||
CPUTriCoreState *env = cs->env_ptr;
|
||||
ctx->mem_idx = cpu_mmu_index(env, false);
|
||||
ctx->hflags = (uint32_t)ctx->base.tb->flags;
|
||||
ctx->features = env->features;
|
||||
}
|
||||
|
||||
static void tricore_tr_tb_start(DisasContextBase *db, CPUState *cpu)
|
||||
|
|
Loading…
Reference in a new issue