target-mips: Add abs2008 flavor of <ABS|NEG>.<S|D>
Updated handling of instructions <ABS|NEG>.<S|D>. Note that legacy (pre-abs2008) ABS and NEG instructions are arithmetic (and, therefore, any NaN operand causes signaling invalid operation), while abs2008 ones are non-arithmetic, always and only changing the sign bit, even for NaN-like operands. Details on these instructions are documented in [1] p. 35 and 359. Implementation-wise, abs2008 versions are implemented without helpers, for simplicity and performance sake. [1] "MIPS Architecture For Programmers Volume II-A: The MIPS64 Instruction Set Reference Manual", Imagination Technologies LTD, Revision 6.04, November 13, 2015 Signed-off-by: Thomas Schwinge <thomas@codesourcery.com> Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com> Signed-off-by: Aleksandar Markovic <aleksandar.markovic@imgtec.com> Reviewed-by: Leon Alrae <leon.alrae@imgtec.com> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
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@ -1435,6 +1435,7 @@ typedef struct DisasContext {
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bool vp;
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bool cmgcr;
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bool mrp;
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bool abs2008;
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} DisasContext;
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enum {
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@ -8890,7 +8891,11 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
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TCGv_i32 fp0 = tcg_temp_new_i32();
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gen_load_fpr32(ctx, fp0, fs);
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gen_helper_float_abs_s(fp0, fp0);
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if (ctx->abs2008) {
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tcg_gen_andi_i32(fp0, fp0, 0x7fffffffUL);
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} else {
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gen_helper_float_abs_s(fp0, fp0);
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}
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gen_store_fpr32(ctx, fp0, fd);
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tcg_temp_free_i32(fp0);
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}
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@ -8909,7 +8914,11 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
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TCGv_i32 fp0 = tcg_temp_new_i32();
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gen_load_fpr32(ctx, fp0, fs);
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gen_helper_float_chs_s(fp0, fp0);
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if (ctx->abs2008) {
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tcg_gen_xori_i32(fp0, fp0, 1UL << 31);
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} else {
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gen_helper_float_chs_s(fp0, fp0);
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}
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gen_store_fpr32(ctx, fp0, fd);
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tcg_temp_free_i32(fp0);
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}
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@ -9380,7 +9389,11 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
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TCGv_i64 fp0 = tcg_temp_new_i64();
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gen_load_fpr64(ctx, fp0, fs);
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gen_helper_float_abs_d(fp0, fp0);
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if (ctx->abs2008) {
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tcg_gen_andi_i64(fp0, fp0, 0x7fffffffffffffffULL);
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} else {
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gen_helper_float_abs_d(fp0, fp0);
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}
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gen_store_fpr64(ctx, fp0, fd);
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tcg_temp_free_i64(fp0);
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}
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@ -9401,7 +9414,11 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
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TCGv_i64 fp0 = tcg_temp_new_i64();
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gen_load_fpr64(ctx, fp0, fs);
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gen_helper_float_chs_d(fp0, fp0);
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if (ctx->abs2008) {
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tcg_gen_xori_i64(fp0, fp0, 1ULL << 63);
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} else {
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gen_helper_float_chs_d(fp0, fp0);
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}
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gen_store_fpr64(ctx, fp0, fd);
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tcg_temp_free_i64(fp0);
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}
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@ -19786,6 +19803,7 @@ void gen_intermediate_code(CPUMIPSState *env, struct TranslationBlock *tb)
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(env->insn_flags & (INSN_LOONGSON2E | INSN_LOONGSON2F));
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ctx.vp = (env->CP0_Config5 >> CP0C5_VP) & 1;
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ctx.mrp = (env->CP0_Config5 >> CP0C5_MRP) & 1;
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ctx.abs2008 = (env->active_fpu.fcr31 >> FCR31_ABS2008) & 1;
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restore_cpu_state(env, &ctx);
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#ifdef CONFIG_USER_ONLY
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ctx.mem_idx = MIPS_HFLAG_UM;
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