Merge remote-tracking branch 'agraf/ppc-for-upstream' into staging
* agraf/ppc-for-upstream: linux-user: Fix invalid TARGET_ABI_BITS usage on ppc hosts target-ppc: Some support for dumping TLB_EMB TLBs ppce500_spin: Replace assert by hw_error (fixes compiler warning) pseries: Fix use of global CPU state pseries: Use the same interrupt swizzling for host bridges as p2p bridges pseries: Implement automatic PAPR VIO address allocation PPC: Fix up e500 cache size setting booke:Use MMU API for creating initial mapping for secondary cpus
This commit is contained in:
Anthony Liguori
commit
6d051a0c56
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@ -86,6 +86,7 @@ static void mmubooke_create_initial_mapping(CPUPPCState *env,
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tlb->mas2 = (va & TARGET_PAGE_MASK) | MAS2_M;
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tlb->mas7_3 = pa & TARGET_PAGE_MASK;
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tlb->mas7_3 |= MAS3_UR | MAS3_UW | MAS3_UX | MAS3_SR | MAS3_SW | MAS3_SX;
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env->tlb_dirty = true;
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}
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static void spin_kick(void *data)
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@ -178,7 +179,7 @@ static uint64_t spin_read(void *opaque, target_phys_addr_t addr, unsigned len)
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case 4:
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return ldl_p(spin_p);
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default:
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assert(0);
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hw_error("ppce500: unexpected %s with len = %u", __func__, len);
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}
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}
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@ -631,8 +631,7 @@ static void ppc_spapr_init(ram_addr_t ram_size,
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for (i = 0; i < MAX_SERIAL_PORTS; i++) {
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if (serial_hds[i]) {
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spapr_vty_create(spapr->vio_bus, SPAPR_VTY_BASE_ADDRESS + i,
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serial_hds[i]);
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spapr_vty_create(spapr->vio_bus, serial_hds[i]);
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}
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}
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@ -650,14 +649,14 @@ static void ppc_spapr_init(ram_addr_t ram_size,
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}
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if (strcmp(nd->model, "ibmveth") == 0) {
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spapr_vlan_create(spapr->vio_bus, 0x1000 + i, nd);
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spapr_vlan_create(spapr->vio_bus, nd);
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} else {
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pci_nic_init_nofail(&nd_table[i], nd->model, NULL);
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}
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}
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for (i = 0; i <= drive_get_max_bus(IF_SCSI); i++) {
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spapr_vscsi_create(spapr->vio_bus, 0x2000 + i);
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spapr_vscsi_create(spapr->vio_bus);
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}
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if (rma_size < (MIN_RMA_SLOF << 20)) {
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@ -482,7 +482,7 @@ static target_ulong register_dtl(CPUPPCState *env, target_ulong addr)
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return H_SUCCESS;
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}
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static target_ulong deregister_dtl(CPUPPCState *emv, target_ulong addr)
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static target_ulong deregister_dtl(CPUPPCState *env, target_ulong addr)
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{
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env->dispatch_trace_log = 0;
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env->dtl_size = 0;
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@ -204,12 +204,11 @@ static int spapr_vlan_init(VIOsPAPRDevice *sdev)
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return 0;
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}
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void spapr_vlan_create(VIOsPAPRBus *bus, uint32_t reg, NICInfo *nd)
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void spapr_vlan_create(VIOsPAPRBus *bus, NICInfo *nd)
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{
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DeviceState *dev;
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dev = qdev_create(&bus->bus, "spapr-vlan");
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qdev_prop_set_uint32(dev, "reg", reg);
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qdev_set_nic_properties(dev, nd);
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@ -480,7 +479,7 @@ static target_ulong h_multicast_ctrl(CPUPPCState *env, sPAPREnvironment *spapr,
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}
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static Property spapr_vlan_properties[] = {
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DEFINE_SPAPR_PROPERTIES(VIOsPAPRVLANDevice, sdev, 0x1000, 0x10000000),
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DEFINE_SPAPR_PROPERTIES(VIOsPAPRVLANDevice, sdev, 0x10000000),
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DEFINE_NIC_PROPERTIES(VIOsPAPRVLANDevice, nicconf),
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DEFINE_PROP_END_OF_LIST(),
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};
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@ -198,16 +198,20 @@ static void rtas_write_pci_config(sPAPREnvironment *spapr,
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finish_write_pci_config(spapr, 0, addr, size, val, rets);
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}
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static int pci_spapr_swizzle(int slot, int pin)
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{
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return (slot + pin) % PCI_NUM_PINS;
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}
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static int pci_spapr_map_irq(PCIDevice *pci_dev, int irq_num)
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{
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/*
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* Here we need to convert pci_dev + irq_num to some unique value
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* which is less than number of IRQs on the specific bus (now it
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* is 16). At the moment irq_num == device_id (number of the
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* slot?)
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* FIXME: we should swizzle in fn and irq_num
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* which is less than number of IRQs on the specific bus (4). We
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* use standard PCI swizzling, that is (slot number + pin number)
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* % 4.
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*/
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return (pci_dev->devfn >> 3) % SPAPR_PCI_NUM_LSI;
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return pci_spapr_swizzle(PCI_SLOT(pci_dev->devfn), irq_num);
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}
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static void pci_spapr_set_irq(void *opaque, int irq_num, int level)
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@ -304,13 +308,13 @@ static int spapr_phb_init(SysBusDevice *s)
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phb->busname ? phb->busname : phb->dtbusname,
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pci_spapr_set_irq, pci_spapr_map_irq, phb,
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&phb->memspace, &phb->iospace,
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PCI_DEVFN(0, 0), SPAPR_PCI_NUM_LSI);
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PCI_DEVFN(0, 0), PCI_NUM_PINS);
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phb->host_state.bus = bus;
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QLIST_INSERT_HEAD(&spapr->phbs, phb, list);
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/* Initialize the LSI table */
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for (i = 0; i < SPAPR_PCI_NUM_LSI; i++) {
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for (i = 0; i < PCI_NUM_PINS; i++) {
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qemu_irq qirq;
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uint32_t num;
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@ -392,8 +396,7 @@ int spapr_populate_pci_devices(sPAPRPHBState *phb,
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uint32_t xics_phandle,
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void *fdt)
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{
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PCIBus *bus = phb->host_state.bus;
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int bus_off, i;
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int bus_off, i, j;
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char nodename[256];
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uint32_t bus_range[] = { cpu_to_be32(0), cpu_to_be32(0xff) };
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struct {
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@ -415,8 +418,8 @@ int spapr_populate_pci_devices(sPAPRPHBState *phb,
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};
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uint64_t bus_reg[] = { cpu_to_be64(phb->buid), 0 };
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uint32_t interrupt_map_mask[] = {
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cpu_to_be32(b_ddddd(-1)|b_fff(0)), 0x0, 0x0, 0x0};
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uint32_t interrupt_map[bus->nirq][7];
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cpu_to_be32(b_ddddd(-1)|b_fff(0)), 0x0, 0x0, cpu_to_be32(-1)};
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uint32_t interrupt_map[PCI_SLOT_MAX * PCI_NUM_PINS][7];
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/* Start populating the FDT */
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sprintf(nodename, "pci@%" PRIx64, phb->buid);
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@ -450,19 +453,23 @@ int spapr_populate_pci_devices(sPAPRPHBState *phb,
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*/
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_FDT(fdt_setprop(fdt, bus_off, "interrupt-map-mask",
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&interrupt_map_mask, sizeof(interrupt_map_mask)));
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for (i = 0; i < 7; i++) {
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uint32_t *irqmap = interrupt_map[i];
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irqmap[0] = cpu_to_be32(b_ddddd(i)|b_fff(0));
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irqmap[1] = 0;
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irqmap[2] = 0;
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irqmap[3] = 0;
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irqmap[4] = cpu_to_be32(xics_phandle);
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irqmap[5] = cpu_to_be32(phb->lsi_table[i % SPAPR_PCI_NUM_LSI].dt_irq);
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irqmap[6] = cpu_to_be32(0x8);
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for (i = 0; i < PCI_SLOT_MAX; i++) {
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for (j = 0; j < PCI_NUM_PINS; j++) {
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uint32_t *irqmap = interrupt_map[i*PCI_NUM_PINS + j];
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int lsi_num = pci_spapr_swizzle(i, j);
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irqmap[0] = cpu_to_be32(b_ddddd(i)|b_fff(0));
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irqmap[1] = 0;
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irqmap[2] = 0;
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irqmap[3] = cpu_to_be32(j+1);
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irqmap[4] = cpu_to_be32(xics_phandle);
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irqmap[5] = cpu_to_be32(phb->lsi_table[lsi_num].dt_irq);
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irqmap[6] = cpu_to_be32(0x8);
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}
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}
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/* Write interrupt map */
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_FDT(fdt_setprop(fdt, bus_off, "interrupt-map", &interrupt_map,
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7 * sizeof(interrupt_map[0])));
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sizeof(interrupt_map)));
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return 0;
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}
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@ -23,11 +23,10 @@
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#if !defined(__HW_SPAPR_PCI_H__)
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#define __HW_SPAPR_PCI_H__
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#include "hw/pci.h"
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#include "hw/pci_host.h"
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#include "hw/xics.h"
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#define SPAPR_PCI_NUM_LSI 16
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typedef struct sPAPRPHBState {
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SysBusDevice busdev;
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PCIHostState host_state;
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@ -43,7 +42,7 @@ typedef struct sPAPRPHBState {
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struct {
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uint32_t dt_irq;
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qemu_irq qirq;
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} lsi_table[SPAPR_PCI_NUM_LSI];
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} lsi_table[PCI_NUM_PINS];
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QLIST_ENTRY(sPAPRPHBState) list;
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} sPAPRPHBState;
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@ -620,28 +620,22 @@ static void rtas_quiesce(sPAPREnvironment *spapr, uint32_t token,
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rtas_st(rets, 0, 0);
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}
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static int spapr_vio_check_reg(VIOsPAPRDevice *sdev)
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static VIOsPAPRDevice *reg_conflict(VIOsPAPRDevice *dev)
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{
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VIOsPAPRDevice *other_sdev;
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VIOsPAPRBus *bus = DO_UPCAST(VIOsPAPRBus, bus, dev->qdev.parent_bus);
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DeviceState *qdev;
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VIOsPAPRBus *sbus;
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sbus = DO_UPCAST(VIOsPAPRBus, bus, sdev->qdev.parent_bus);
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VIOsPAPRDevice *other;
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/*
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* Check two device aren't given clashing addresses by the user (or some
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* other mechanism). We have to open code this because we have to check
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* for matches with devices other than us.
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* Check for a device other than the given one which is already
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* using the requested address. We have to open code this because
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* the given dev might already be in the list.
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*/
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QTAILQ_FOREACH(qdev, &sbus->bus.children, sibling) {
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other_sdev = DO_UPCAST(VIOsPAPRDevice, qdev, qdev);
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QTAILQ_FOREACH(qdev, &bus->bus.children, sibling) {
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other = DO_UPCAST(VIOsPAPRDevice, qdev, qdev);
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if (other_sdev != sdev && other_sdev->reg == sdev->reg) {
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fprintf(stderr, "vio: %s and %s devices conflict at address %#x\n",
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object_get_typename(OBJECT(sdev)),
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object_get_typename(OBJECT(qdev)),
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sdev->reg);
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return -EEXIST;
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if (other != dev && other->reg == dev->reg) {
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return other;
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}
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}
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@ -667,11 +661,30 @@ static int spapr_vio_busdev_init(DeviceState *qdev)
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VIOsPAPRDevice *dev = (VIOsPAPRDevice *)qdev;
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VIOsPAPRDeviceClass *pc = VIO_SPAPR_DEVICE_GET_CLASS(dev);
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char *id;
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int ret;
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ret = spapr_vio_check_reg(dev);
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if (ret) {
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return ret;
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if (dev->reg != -1) {
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/*
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* Explicitly assigned address, just verify that no-one else
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* is using it. other mechanism). We have to open code this
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* rather than using spapr_vio_find_by_reg() because sdev
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* itself is already in the list.
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*/
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VIOsPAPRDevice *other = reg_conflict(dev);
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if (other) {
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fprintf(stderr, "vio: %s and %s devices conflict at address %#x\n",
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object_get_typename(OBJECT(qdev)),
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object_get_typename(OBJECT(&other->qdev)),
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dev->reg);
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return -1;
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}
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} else {
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/* Need to assign an address */
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VIOsPAPRBus *bus = DO_UPCAST(VIOsPAPRBus, bus, dev->qdev.parent_bus);
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do {
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dev->reg = bus->next_reg++;
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} while (reg_conflict(dev));
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}
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/* Don't overwrite ids assigned on the command line */
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@ -731,6 +744,7 @@ VIOsPAPRBus *spapr_vio_bus_init(void)
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qbus = qbus_create(&spapr_vio_bus_info, dev, "spapr-vio");
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bus = DO_UPCAST(VIOsPAPRBus, bus, qbus);
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bus->next_reg = 0x1000;
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/* hcall-vio */
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spapr_register_hypercall(H_VIO_SIGNAL, h_vio_signal);
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@ -32,8 +32,6 @@ enum VIOsPAPR_TCEAccess {
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SPAPR_TCE_RW = 3,
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};
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#define SPAPR_VTY_BASE_ADDRESS 0x30000000
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#define TYPE_VIO_SPAPR_DEVICE "vio-spapr-device"
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#define VIO_SPAPR_DEVICE(obj) \
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OBJECT_CHECK(VIOsPAPRDevice, (obj), TYPE_VIO_SPAPR_DEVICE)
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@ -82,13 +80,14 @@ struct VIOsPAPRDevice {
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VIOsPAPR_CRQ crq;
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};
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#define DEFINE_SPAPR_PROPERTIES(type, field, default_reg, default_dma_window) \
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DEFINE_PROP_UINT32("reg", type, field.reg, default_reg), \
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#define DEFINE_SPAPR_PROPERTIES(type, field, default_dma_window) \
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DEFINE_PROP_UINT32("reg", type, field.reg, -1), \
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DEFINE_PROP_UINT32("dma-window", type, field.rtce_window_size, \
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default_dma_window)
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struct VIOsPAPRBus {
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BusState bus;
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uint32_t next_reg;
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int (*init)(VIOsPAPRDevice *dev);
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int (*devnode)(VIOsPAPRDevice *dev, void *fdt, int node_off);
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};
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@ -119,9 +118,9 @@ int spapr_vio_send_crq(VIOsPAPRDevice *dev, uint8_t *crq);
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VIOsPAPRDevice *vty_lookup(sPAPREnvironment *spapr, target_ulong reg);
|
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void vty_putchars(VIOsPAPRDevice *sdev, uint8_t *buf, int len);
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void spapr_vty_create(VIOsPAPRBus *bus, uint32_t reg, CharDriverState *chardev);
|
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void spapr_vlan_create(VIOsPAPRBus *bus, uint32_t reg, NICInfo *nd);
|
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void spapr_vscsi_create(VIOsPAPRBus *bus, uint32_t reg);
|
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void spapr_vty_create(VIOsPAPRBus *bus, CharDriverState *chardev);
|
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void spapr_vlan_create(VIOsPAPRBus *bus, NICInfo *nd);
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void spapr_vscsi_create(VIOsPAPRBus *bus);
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VIOsPAPRDevice *spapr_vty_get_default(VIOsPAPRBus *bus);
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|
|
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@ -918,12 +918,11 @@ static int spapr_vscsi_init(VIOsPAPRDevice *dev)
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return 0;
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}
|
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|
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void spapr_vscsi_create(VIOsPAPRBus *bus, uint32_t reg)
|
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void spapr_vscsi_create(VIOsPAPRBus *bus)
|
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{
|
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DeviceState *dev;
|
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|
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dev = qdev_create(&bus->bus, "spapr-vscsi");
|
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qdev_prop_set_uint32(dev, "reg", reg);
|
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qdev_init_nofail(dev);
|
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}
|
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|
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@ -946,7 +945,7 @@ static int spapr_vscsi_devnode(VIOsPAPRDevice *dev, void *fdt, int node_off)
|
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}
|
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|
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static Property spapr_vscsi_properties[] = {
|
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DEFINE_SPAPR_PROPERTIES(VSCSIState, vdev, 0x2000, 0x10000000),
|
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DEFINE_SPAPR_PROPERTIES(VSCSIState, vdev, 0x10000000),
|
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DEFINE_PROP_END_OF_LIST(),
|
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};
|
||||
|
||||
|
|
|
|||
|
|
@ -123,18 +123,17 @@ static target_ulong h_get_term_char(CPUPPCState *env, sPAPREnvironment *spapr,
|
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return H_SUCCESS;
|
||||
}
|
||||
|
||||
void spapr_vty_create(VIOsPAPRBus *bus, uint32_t reg, CharDriverState *chardev)
|
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void spapr_vty_create(VIOsPAPRBus *bus, CharDriverState *chardev)
|
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{
|
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DeviceState *dev;
|
||||
|
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dev = qdev_create(&bus->bus, "spapr-vty");
|
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qdev_prop_set_uint32(dev, "reg", reg);
|
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qdev_prop_set_chr(dev, "chardev", chardev);
|
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qdev_init_nofail(dev);
|
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}
|
||||
|
||||
static Property spapr_vty_properties[] = {
|
||||
DEFINE_SPAPR_PROPERTIES(VIOsPAPRVTYDevice, sdev, SPAPR_VTY_BASE_ADDRESS, 0),
|
||||
DEFINE_SPAPR_PROPERTIES(VIOsPAPRVTYDevice, sdev, 0),
|
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DEFINE_PROP_CHR("chardev", VIOsPAPRVTYDevice, chardev),
|
||||
DEFINE_PROP_END_OF_LIST(),
|
||||
};
|
||||
|
|
|
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|
|
@ -1466,6 +1466,53 @@ static const char *book3e_tsize_to_str[32] = {
|
|||
"1T", "2T"
|
||||
};
|
||||
|
||||
static void mmubooke_dump_mmu(FILE *f, fprintf_function cpu_fprintf,
|
||||
CPUPPCState *env)
|
||||
{
|
||||
ppcemb_tlb_t *entry;
|
||||
int i;
|
||||
|
||||
if (kvm_enabled() && !env->kvm_sw_tlb) {
|
||||
cpu_fprintf(f, "Cannot access KVM TLB\n");
|
||||
return;
|
||||
}
|
||||
|
||||
cpu_fprintf(f, "\nTLB:\n");
|
||||
cpu_fprintf(f, "Effective Physical Size PID Prot "
|
||||
"Attr\n");
|
||||
|
||||
entry = &env->tlb.tlbe[0];
|
||||
for (i = 0; i < env->nb_tlb; i++, entry++) {
|
||||
target_phys_addr_t ea, pa;
|
||||
target_ulong mask;
|
||||
uint64_t size = (uint64_t)entry->size;
|
||||
char size_buf[20];
|
||||
|
||||
/* Check valid flag */
|
||||
if (!(entry->prot & PAGE_VALID)) {
|
||||
continue;
|
||||
}
|
||||
|
||||
mask = ~(entry->size - 1);
|
||||
ea = entry->EPN & mask;
|
||||
pa = entry->RPN & mask;
|
||||
#if (TARGET_PHYS_ADDR_BITS >= 36)
|
||||
/* Extend the physical address to 36 bits */
|
||||
pa |= (target_phys_addr_t)(entry->RPN & 0xF) << 32;
|
||||
#endif
|
||||
size /= 1024;
|
||||
if (size >= 1024) {
|
||||
snprintf(size_buf, sizeof(size_buf), "%3" PRId64 "M", size / 1024);
|
||||
} else {
|
||||
snprintf(size_buf, sizeof(size_buf), "%3" PRId64 "k", size);
|
||||
}
|
||||
cpu_fprintf(f, "0x%016" PRIx64 " 0x%016" PRIx64 " %s %-5u %08x %08x\n",
|
||||
(uint64_t)ea, (uint64_t)pa, size_buf, (uint32_t)entry->PID,
|
||||
entry->prot, entry->attr);
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
static void mmubooke206_dump_one_tlb(FILE *f, fprintf_function cpu_fprintf,
|
||||
CPUPPCState *env, int tlbn, int offset,
|
||||
int tlbsize)
|
||||
|
|
@ -1561,6 +1608,9 @@ static void mmubooks_dump_mmu(FILE *f, fprintf_function cpu_fprintf,
|
|||
void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUPPCState *env)
|
||||
{
|
||||
switch (env->mmu_model) {
|
||||
case POWERPC_MMU_BOOKE:
|
||||
mmubooke_dump_mmu(f, cpu_fprintf, env);
|
||||
break;
|
||||
case POWERPC_MMU_BOOKE206:
|
||||
mmubooke206_dump_mmu(f, cpu_fprintf, env);
|
||||
break;
|
||||
|
|
|
|||
|
|
@ -4461,33 +4461,36 @@ static void init_proc_e500 (CPUPPCState *env, int version)
|
|||
&spr_read_spefscr, &spr_write_spefscr,
|
||||
&spr_read_spefscr, &spr_write_spefscr,
|
||||
0x00000000);
|
||||
#if !defined(CONFIG_USER_ONLY)
|
||||
/* Memory management */
|
||||
#if defined(CONFIG_USER_ONLY)
|
||||
env->dcache_line_size = 32;
|
||||
env->icache_line_size = 32;
|
||||
#else /* !defined(CONFIG_USER_ONLY) */
|
||||
env->nb_pids = 3;
|
||||
env->nb_ways = 2;
|
||||
env->id_tlbs = 0;
|
||||
switch (version) {
|
||||
case fsl_e500v1:
|
||||
/* e500v1 */
|
||||
tlbncfg[0] = gen_tlbncfg(2, 1, 1, 0, 256);
|
||||
tlbncfg[1] = gen_tlbncfg(16, 1, 9, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16);
|
||||
env->dcache_line_size = 32;
|
||||
env->icache_line_size = 32;
|
||||
break;
|
||||
case fsl_e500v2:
|
||||
/* e500v2 */
|
||||
tlbncfg[0] = gen_tlbncfg(4, 1, 1, 0, 512);
|
||||
tlbncfg[1] = gen_tlbncfg(16, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16);
|
||||
break;
|
||||
case fsl_e500mc:
|
||||
tlbncfg[0] = gen_tlbncfg(4, 1, 1, 0, 512);
|
||||
tlbncfg[1] = gen_tlbncfg(64, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 64);
|
||||
break;
|
||||
default:
|
||||
cpu_abort(env, "Unknown CPU: " TARGET_FMT_lx "\n", env->spr[SPR_PVR]);
|
||||
}
|
||||
#endif
|
||||
/* Cache sizes */
|
||||
switch (version) {
|
||||
case fsl_e500v1:
|
||||
case fsl_e500v2:
|
||||
env->dcache_line_size = 32;
|
||||
env->icache_line_size = 32;
|
||||
break;
|
||||
case fsl_e500mc:
|
||||
/* e500mc */
|
||||
tlbncfg[0] = gen_tlbncfg(4, 1, 1, 0, 512);
|
||||
tlbncfg[1] = gen_tlbncfg(64, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 64);
|
||||
env->dcache_line_size = 64;
|
||||
env->icache_line_size = 64;
|
||||
l1cfg0 |= 0x1000000; /* 64 byte cache block size */
|
||||
|
|
@ -4495,7 +4498,6 @@ static void init_proc_e500 (CPUPPCState *env, int version)
|
|||
default:
|
||||
cpu_abort(env, "Unknown CPU: " TARGET_FMT_lx "\n", env->spr[SPR_PVR]);
|
||||
}
|
||||
#endif
|
||||
gen_spr_BookE206(env, 0x000000DF, tlbncfg);
|
||||
/* XXX : not implemented */
|
||||
spr_register(env, SPR_HID0, "HID0",
|
||||
|
|
|
|||
Loading…
Reference in a new issue