hw/misc/bcm2835_cprman: implement PLLs behaviour
The CPRMAN PLLs generate a clock based on a prescaler, a multiplier and a divider. The prescaler doubles the parent (xosc) frequency, then the multiplier/divider are applied. The multiplier has an integer and a fractional part. This commit also implements the CPRMAN CM_LOCK register. This register reports which PLL is currently locked. We consider a PLL has being locked as soon as it is enabled (on real hardware, there is a delay after turning a PLL on, for it to stabilize). Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Luc Michel <luc@lmichel.fr> Tested-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@ -50,9 +50,47 @@
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/* PLL */
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static bool pll_is_locked(const CprmanPllState *pll)
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{
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return !FIELD_EX32(*pll->reg_a2w_ctrl, A2W_PLLx_CTRL, PWRDN)
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&& !FIELD_EX32(*pll->reg_cm, CM_PLLx, ANARST);
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}
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static void pll_update(CprmanPllState *pll)
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{
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clock_update(pll->out, 0);
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uint64_t freq, ndiv, fdiv, pdiv;
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if (!pll_is_locked(pll)) {
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clock_update(pll->out, 0);
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return;
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}
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pdiv = FIELD_EX32(*pll->reg_a2w_ctrl, A2W_PLLx_CTRL, PDIV);
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if (!pdiv) {
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clock_update(pll->out, 0);
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return;
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}
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ndiv = FIELD_EX32(*pll->reg_a2w_ctrl, A2W_PLLx_CTRL, NDIV);
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fdiv = FIELD_EX32(*pll->reg_a2w_frac, A2W_PLLx_FRAC, FRAC);
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if (pll->reg_a2w_ana[1] & pll->prediv_mask) {
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/* The prescaler doubles the parent frequency */
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ndiv *= 2;
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fdiv *= 2;
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}
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/*
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* We have a multiplier with an integer part (ndiv) and a fractional part
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* (fdiv), and a divider (pdiv).
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*/
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freq = clock_get_hz(pll->xosc_in) *
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((ndiv << R_A2W_PLLx_FRAC_FRAC_LENGTH) + fdiv);
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freq /= pdiv;
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freq >>= R_A2W_PLLx_FRAC_FRAC_LENGTH;
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clock_update_hz(pll->out, freq);
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}
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static void pll_xosc_update(void *opaque)
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@ -96,6 +134,26 @@ static const TypeInfo cprman_pll_info = {
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/* CPRMAN "top level" model */
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static uint32_t get_cm_lock(const BCM2835CprmanState *s)
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{
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static const int CM_LOCK_MAPPING[CPRMAN_NUM_PLL] = {
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[CPRMAN_PLLA] = R_CM_LOCK_FLOCKA_SHIFT,
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[CPRMAN_PLLC] = R_CM_LOCK_FLOCKC_SHIFT,
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[CPRMAN_PLLD] = R_CM_LOCK_FLOCKD_SHIFT,
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[CPRMAN_PLLH] = R_CM_LOCK_FLOCKH_SHIFT,
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[CPRMAN_PLLB] = R_CM_LOCK_FLOCKB_SHIFT,
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};
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uint32_t r = 0;
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size_t i;
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for (i = 0; i < CPRMAN_NUM_PLL; i++) {
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r |= pll_is_locked(&s->plls[i]) << CM_LOCK_MAPPING[i];
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}
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return r;
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}
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static uint64_t cprman_read(void *opaque, hwaddr offset,
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unsigned size)
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{
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@ -104,6 +162,10 @@ static uint64_t cprman_read(void *opaque, hwaddr offset,
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size_t idx = offset / sizeof(uint32_t);
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switch (idx) {
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case R_CM_LOCK:
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r = get_cm_lock(s);
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break;
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default:
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r = s->regs[idx];
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}
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@ -100,6 +100,14 @@ REG32(A2W_PLLD_FRAC, 0x1240)
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REG32(A2W_PLLH_FRAC, 0x1260)
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REG32(A2W_PLLB_FRAC, 0x12e0)
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/* misc registers */
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REG32(CM_LOCK, 0x114)
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FIELD(CM_LOCK, FLOCKH, 12, 1)
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FIELD(CM_LOCK, FLOCKD, 11, 1)
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FIELD(CM_LOCK, FLOCKC, 10, 1)
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FIELD(CM_LOCK, FLOCKB, 9, 1)
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FIELD(CM_LOCK, FLOCKA, 8, 1)
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/*
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* This field is common to all registers. Each register write value must match
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* the CPRMAN_PASSWORD magic value in its 8 MSB.
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