-----BEGIN PGP SIGNATURE----- iQFRBAABCgA7FiEEekgeeIaLTbaoWgXAZN846K9+IV8FAlzhaMkdHHJpY2hhcmQu aGVuZGVyc29uQGxpbmFyby5vcmcACgkQZN846K9+IV9n2ggAuV7yVpFOaPgN901M w0pk/bCOq9mOO2O6YVE2Y+m4iEML6hU+yBIHkxP1AIzltxDf6zhFMhRT/Q4wxvvg h7w1zVWtqhQ5YDVh6q1Bk7Cgz0/CMrG1m/ADNZns/zYTFLObRdJOudN67HTxKFeF qh9IxbfYkmUccqsRTi9j0IEjgMA7ldnHHMRjf8du9cJo1rePn3SUVREv3XwZRtMd lS6uL67C2dLs8nPnCXNpJF7ZA8PmrBAOlsKsVrd7zisUPrItPnO99P0DewemIPZd 1MwliwNs3xN+F64K6HsItaOoqgskiBoTX0ZrATSFJB0xRS0N/AMuxg8jHahenMlC Pdjcww== =lUbY -----END PGP SIGNATURE----- Merge remote-tracking branch 'remotes/rth/tags/pull-axp-20190519' into staging Fix https://bugs.launchpad.net/bugs/1701835 # gpg: Signature made Sun 19 May 2019 15:31:37 BST # gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F # gpg: issuer "richard.henderson@linaro.org" # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full] # Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F * remotes/rth/tags/pull-axp-20190519: target/alpha: Fix user-only floating-point exceptions target/alpha: Clean up alpha_cpu_dump_state Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell
commit
6d8e75d41c
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@ -10223,18 +10223,11 @@ static abi_long do_syscall1(void *cpu_env, int num, abi_long arg1,
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switch (arg1) {
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case TARGET_GSI_IEEE_FP_CONTROL:
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{
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uint64_t swcr, fpcr = cpu_alpha_load_fpcr (cpu_env);
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uint64_t fpcr = cpu_alpha_load_fpcr(cpu_env);
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uint64_t swcr = ((CPUAlphaState *)cpu_env)->swcr;
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/* Copied from linux ieee_fpcr_to_swcr. */
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swcr = (fpcr >> 35) & SWCR_STATUS_MASK;
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swcr |= (fpcr >> 36) & SWCR_MAP_DMZ;
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swcr |= (~fpcr >> 48) & (SWCR_TRAP_ENABLE_INV
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| SWCR_TRAP_ENABLE_DZE
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| SWCR_TRAP_ENABLE_OVF);
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swcr |= (~fpcr >> 57) & (SWCR_TRAP_ENABLE_UNF
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| SWCR_TRAP_ENABLE_INE);
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swcr |= (fpcr >> 47) & SWCR_MAP_UMZ;
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swcr |= (~fpcr >> 41) & SWCR_TRAP_ENABLE_DNO;
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swcr &= ~SWCR_STATUS_MASK;
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swcr |= (fpcr >> 35) & SWCR_STATUS_MASK;
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if (put_user_u64 (swcr, arg2))
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return -TARGET_EFAULT;
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@ -10261,25 +10254,24 @@ static abi_long do_syscall1(void *cpu_env, int num, abi_long arg1,
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switch (arg1) {
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case TARGET_SSI_IEEE_FP_CONTROL:
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{
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uint64_t swcr, fpcr, orig_fpcr;
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uint64_t swcr, fpcr;
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if (get_user_u64 (swcr, arg2)) {
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return -TARGET_EFAULT;
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}
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orig_fpcr = cpu_alpha_load_fpcr(cpu_env);
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fpcr = orig_fpcr & FPCR_DYN_MASK;
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/* Copied from linux ieee_swcr_to_fpcr. */
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fpcr |= (swcr & SWCR_STATUS_MASK) << 35;
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fpcr |= (swcr & SWCR_MAP_DMZ) << 36;
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fpcr |= (~swcr & (SWCR_TRAP_ENABLE_INV
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| SWCR_TRAP_ENABLE_DZE
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| SWCR_TRAP_ENABLE_OVF)) << 48;
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fpcr |= (~swcr & (SWCR_TRAP_ENABLE_UNF
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| SWCR_TRAP_ENABLE_INE)) << 57;
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fpcr |= (swcr & SWCR_MAP_UMZ ? FPCR_UNDZ | FPCR_UNFD : 0);
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fpcr |= (~swcr & SWCR_TRAP_ENABLE_DNO) << 41;
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/*
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* The kernel calls swcr_update_status to update the
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* status bits from the fpcr at every point that it
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* could be queried. Therefore, we store the status
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* bits only in FPCR.
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*/
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((CPUAlphaState *)cpu_env)->swcr
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= swcr & (SWCR_TRAP_ENABLE_MASK | SWCR_MAP_MASK);
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fpcr = cpu_alpha_load_fpcr(cpu_env);
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fpcr &= ((uint64_t)FPCR_DYN_MASK << 32);
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fpcr |= alpha_ieee_swcr_to_fpcr(swcr);
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cpu_alpha_store_fpcr(cpu_env, fpcr);
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ret = 0;
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}
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@ -10287,44 +10279,47 @@ static abi_long do_syscall1(void *cpu_env, int num, abi_long arg1,
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case TARGET_SSI_IEEE_RAISE_EXCEPTION:
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{
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uint64_t exc, fpcr, orig_fpcr;
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int si_code;
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uint64_t exc, fpcr, fex;
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if (get_user_u64(exc, arg2)) {
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return -TARGET_EFAULT;
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}
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orig_fpcr = cpu_alpha_load_fpcr(cpu_env);
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/* We only add to the exception status here. */
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fpcr = orig_fpcr | ((exc & SWCR_STATUS_MASK) << 35);
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cpu_alpha_store_fpcr(cpu_env, fpcr);
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ret = 0;
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exc &= SWCR_STATUS_MASK;
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fpcr = cpu_alpha_load_fpcr(cpu_env);
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/* Old exceptions are not signaled. */
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fpcr &= ~(orig_fpcr & FPCR_STATUS_MASK);
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fex = alpha_ieee_fpcr_to_swcr(fpcr);
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fex = exc & ~fex;
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fex >>= SWCR_STATUS_TO_EXCSUM_SHIFT;
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fex &= ((CPUArchState *)cpu_env)->swcr;
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/* If any exceptions set by this call,
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and are unmasked, send a signal. */
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si_code = 0;
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if ((fpcr & (FPCR_INE | FPCR_INED)) == FPCR_INE) {
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si_code = TARGET_FPE_FLTRES;
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}
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if ((fpcr & (FPCR_UNF | FPCR_UNFD)) == FPCR_UNF) {
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si_code = TARGET_FPE_FLTUND;
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}
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if ((fpcr & (FPCR_OVF | FPCR_OVFD)) == FPCR_OVF) {
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si_code = TARGET_FPE_FLTOVF;
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}
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if ((fpcr & (FPCR_DZE | FPCR_DZED)) == FPCR_DZE) {
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si_code = TARGET_FPE_FLTDIV;
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}
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if ((fpcr & (FPCR_INV | FPCR_INVD)) == FPCR_INV) {
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si_code = TARGET_FPE_FLTINV;
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}
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if (si_code != 0) {
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/* Update the hardware fpcr. */
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fpcr |= alpha_ieee_swcr_to_fpcr(exc);
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cpu_alpha_store_fpcr(cpu_env, fpcr);
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if (fex) {
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int si_code = TARGET_FPE_FLTUNK;
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target_siginfo_t info;
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if (fex & SWCR_TRAP_ENABLE_DNO) {
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si_code = TARGET_FPE_FLTUND;
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}
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if (fex & SWCR_TRAP_ENABLE_INE) {
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si_code = TARGET_FPE_FLTRES;
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}
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if (fex & SWCR_TRAP_ENABLE_UNF) {
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si_code = TARGET_FPE_FLTUND;
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}
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if (fex & SWCR_TRAP_ENABLE_OVF) {
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si_code = TARGET_FPE_FLTOVF;
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}
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if (fex & SWCR_TRAP_ENABLE_DZE) {
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si_code = TARGET_FPE_FLTDIV;
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}
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if (fex & SWCR_TRAP_ENABLE_INV) {
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si_code = TARGET_FPE_FLTINV;
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}
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info.si_signo = SIGFPE;
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info.si_errno = 0;
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info.si_code = si_code;
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@ -10333,6 +10328,7 @@ static abi_long do_syscall1(void *cpu_env, int num, abi_long arg1,
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queue_signal((CPUArchState *)cpu_env, info.si_signo,
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QEMU_SI_FAULT, &info);
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}
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ret = 0;
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}
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break;
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@ -635,7 +635,8 @@ typedef struct target_siginfo {
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#define TARGET_FPE_FLTRES (6) /* floating point inexact result */
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#define TARGET_FPE_FLTINV (7) /* floating point invalid operation */
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#define TARGET_FPE_FLTSUB (8) /* subscript out of range */
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#define TARGET_NSIGFPE 8
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#define TARGET_FPE_FLTUNK (14) /* undiagnosed fp exception */
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#define TARGET_NSIGFPE 15
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/*
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* SIGSEGV si_codes
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@ -198,6 +198,8 @@ enum {
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#define SWCR_STATUS_DNO (1U << 22)
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#define SWCR_STATUS_MASK ((1U << 23) - (1U << 17))
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#define SWCR_STATUS_TO_EXCSUM_SHIFT 16
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#define SWCR_MASK (SWCR_TRAP_ENABLE_MASK | SWCR_MAP_MASK | SWCR_STATUS_MASK)
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/* MMU modes definitions */
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@ -235,6 +237,9 @@ struct CPUAlphaState {
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/* The FPCR, and disassembled portions thereof. */
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uint32_t fpcr;
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#ifdef CONFIG_USER_ONLY
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uint32_t swcr;
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#endif
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uint32_t fpcr_exc_enable;
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float_status fp_status;
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uint8_t fpcr_dyn_round;
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@ -501,4 +506,41 @@ static inline void cpu_get_tb_cpu_state(CPUAlphaState *env, target_ulong *pc,
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*pflags = env->flags & ENV_FLAG_TB_MASK;
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}
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#ifdef CONFIG_USER_ONLY
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/* Copied from linux ieee_swcr_to_fpcr. */
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static inline uint64_t alpha_ieee_swcr_to_fpcr(uint64_t swcr)
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{
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uint64_t fpcr = 0;
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fpcr |= (swcr & SWCR_STATUS_MASK) << 35;
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fpcr |= (swcr & SWCR_MAP_DMZ) << 36;
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fpcr |= (~swcr & (SWCR_TRAP_ENABLE_INV
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| SWCR_TRAP_ENABLE_DZE
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| SWCR_TRAP_ENABLE_OVF)) << 48;
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fpcr |= (~swcr & (SWCR_TRAP_ENABLE_UNF
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| SWCR_TRAP_ENABLE_INE)) << 57;
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fpcr |= (swcr & SWCR_MAP_UMZ ? FPCR_UNDZ | FPCR_UNFD : 0);
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fpcr |= (~swcr & SWCR_TRAP_ENABLE_DNO) << 41;
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return fpcr;
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}
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/* Copied from linux ieee_fpcr_to_swcr. */
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static inline uint64_t alpha_ieee_fpcr_to_swcr(uint64_t fpcr)
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{
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uint64_t swcr = 0;
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swcr |= (fpcr >> 35) & SWCR_STATUS_MASK;
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swcr |= (fpcr >> 36) & SWCR_MAP_DMZ;
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swcr |= (~fpcr >> 48) & (SWCR_TRAP_ENABLE_INV
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| SWCR_TRAP_ENABLE_DZE
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| SWCR_TRAP_ENABLE_OVF);
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swcr |= (~fpcr >> 57) & (SWCR_TRAP_ENABLE_UNF | SWCR_TRAP_ENABLE_INE);
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swcr |= (fpcr >> 47) & SWCR_MAP_UMZ;
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swcr |= (~fpcr >> 41) & SWCR_TRAP_ENABLE_DNO;
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return swcr;
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}
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#endif /* CONFIG_USER_ONLY */
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#endif /* ALPHA_CPU_H */
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@ -91,10 +91,25 @@ void helper_fp_exc_raise_s(CPUAlphaState *env, uint32_t ignore, uint32_t regno)
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if (exc) {
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env->fpcr |= exc;
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exc &= ~ignore;
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if (exc) {
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exc &= env->fpcr_exc_enable;
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fp_exc_raise1(env, GETPC(), exc, regno, EXC_M_SWC);
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#ifdef CONFIG_USER_ONLY
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/*
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* In user mode, the kernel's software handler only
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* delivers a signal if the exception is enabled.
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*/
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if (!(exc & env->fpcr_exc_enable)) {
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return;
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}
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#else
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/*
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* In system mode, the software handler gets invoked
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* for any non-ignored exception.
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*/
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if (!exc) {
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return;
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}
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#endif
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exc &= env->fpcr_exc_enable;
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fp_exc_raise1(env, GETPC(), exc, regno, EXC_M_SWC);
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}
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}
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@ -29,12 +29,12 @@
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#define CONVERT_BIT(X, SRC, DST) \
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(SRC > DST ? (X) / (SRC / DST) & (DST) : ((X) & SRC) * (DST / SRC))
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uint64_t cpu_alpha_load_fpcr (CPUAlphaState *env)
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uint64_t cpu_alpha_load_fpcr(CPUAlphaState *env)
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{
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return (uint64_t)env->fpcr << 32;
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}
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void cpu_alpha_store_fpcr (CPUAlphaState *env, uint64_t val)
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void cpu_alpha_store_fpcr(CPUAlphaState *env, uint64_t val)
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{
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uint32_t fpcr = val >> 32;
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uint32_t t = 0;
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@ -67,6 +67,22 @@ void cpu_alpha_store_fpcr (CPUAlphaState *env, uint64_t val)
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env->fpcr_flush_to_zero = (fpcr & FPCR_UNFD) && (fpcr & FPCR_UNDZ);
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env->fp_status.flush_inputs_to_zero = (fpcr & FPCR_DNZ) != 0;
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#ifdef CONFIG_USER_ONLY
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/*
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* Override some of these bits with the contents of ENV->SWCR.
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* In system mode, some of these would trap to the kernel, at
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* which point the kernel's handler would emulate and apply
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* the software exception mask.
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*/
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if (env->swcr & SWCR_MAP_DMZ) {
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env->fp_status.flush_inputs_to_zero = 1;
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}
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if (env->swcr & SWCR_MAP_UMZ) {
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env->fp_status.flush_to_zero = 1;
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}
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env->fpcr_exc_enable &= ~(alpha_ieee_swcr_to_fpcr(env->swcr) >> 32);
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#endif
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}
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uint64_t helper_load_fpcr(CPUAlphaState *env)
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@ -435,32 +451,33 @@ bool alpha_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
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void alpha_cpu_dump_state(CPUState *cs, FILE *f, int flags)
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{
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static const char *linux_reg_names[] = {
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"v0 ", "t0 ", "t1 ", "t2 ", "t3 ", "t4 ", "t5 ", "t6 ",
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"t7 ", "s0 ", "s1 ", "s2 ", "s3 ", "s4 ", "s5 ", "fp ",
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"a0 ", "a1 ", "a2 ", "a3 ", "a4 ", "a5 ", "t8 ", "t9 ",
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"t10", "t11", "ra ", "t12", "at ", "gp ", "sp ", "zero",
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static const char linux_reg_names[31][4] = {
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"v0", "t0", "t1", "t2", "t3", "t4", "t5", "t6",
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"t7", "s0", "s1", "s2", "s3", "s4", "s5", "fp",
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"a0", "a1", "a2", "a3", "a4", "a5", "t8", "t9",
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"t10", "t11", "ra", "t12", "at", "gp", "sp"
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};
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AlphaCPU *cpu = ALPHA_CPU(cs);
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CPUAlphaState *env = &cpu->env;
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int i;
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qemu_fprintf(f, " PC " TARGET_FMT_lx " PS %02x\n",
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qemu_fprintf(f, "PC " TARGET_FMT_lx " PS %02x\n",
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env->pc, extract32(env->flags, ENV_FLAG_PS_SHIFT, 8));
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for (i = 0; i < 31; i++) {
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qemu_fprintf(f, "IR%02d %s " TARGET_FMT_lx "%c", i,
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qemu_fprintf(f, "%-8s" TARGET_FMT_lx "%c",
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linux_reg_names[i], cpu_alpha_load_gr(env, i),
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(i % 3) == 2 ? '\n' : ' ');
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}
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qemu_fprintf(f, "lock_a " TARGET_FMT_lx " lock_v " TARGET_FMT_lx "\n",
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qemu_fprintf(f, "lock_a " TARGET_FMT_lx " lock_v " TARGET_FMT_lx "\n",
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env->lock_addr, env->lock_value);
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if (flags & CPU_DUMP_FPU) {
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for (i = 0; i < 31; i++) {
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qemu_fprintf(f, "FIR%02d %016" PRIx64 "%c", i, env->fir[i],
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qemu_fprintf(f, "f%-7d%016" PRIx64 "%c", i, env->fir[i],
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(i % 3) == 2 ? '\n' : ' ');
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}
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qemu_fprintf(f, "fpcr %016" PRIx64 "\n", cpu_alpha_load_fpcr(env));
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}
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qemu_fprintf(f, "\n");
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}
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