RISC-V: fix single stepping over ret and other branching instructions
This patch introduces wrappers around the tcg_gen_exit_tb() and tcg_gen_lookup_and_goto_ptr() functions that handle single stepping, i.e. call gen_exception_debug() when single stepping is enabled. Theses functions are then used instead of the originals, bringing single stepping handling in places where it was previously ignored such as jalr and system branch instructions (ecall, mret, sret, etc.). Signed-off-by: Fabien Chouteau <chouteau@adacore.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
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@ -22,7 +22,7 @@ static bool trans_ecall(DisasContext *ctx, arg_ecall *a)
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{
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/* always generates U-level ECALL, fixed in do_interrupt handler */
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generate_exception(ctx, RISCV_EXCP_U_ECALL);
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tcg_gen_exit_tb(NULL, 0); /* no chaining */
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exit_tb(ctx); /* no chaining */
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ctx->base.is_jmp = DISAS_NORETURN;
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return true;
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}
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@ -30,7 +30,7 @@ static bool trans_ecall(DisasContext *ctx, arg_ecall *a)
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static bool trans_ebreak(DisasContext *ctx, arg_ebreak *a)
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{
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generate_exception(ctx, RISCV_EXCP_BREAKPOINT);
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tcg_gen_exit_tb(NULL, 0); /* no chaining */
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exit_tb(ctx); /* no chaining */
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ctx->base.is_jmp = DISAS_NORETURN;
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return true;
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}
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@ -47,7 +47,7 @@ static bool trans_sret(DisasContext *ctx, arg_sret *a)
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if (has_ext(ctx, RVS)) {
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gen_helper_sret(cpu_pc, cpu_env, cpu_pc);
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tcg_gen_exit_tb(NULL, 0); /* no chaining */
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exit_tb(ctx); /* no chaining */
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ctx->base.is_jmp = DISAS_NORETURN;
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} else {
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return false;
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@ -68,7 +68,7 @@ static bool trans_mret(DisasContext *ctx, arg_mret *a)
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#ifndef CONFIG_USER_ONLY
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tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next);
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gen_helper_mret(cpu_pc, cpu_env, cpu_pc);
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tcg_gen_exit_tb(NULL, 0); /* no chaining */
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exit_tb(ctx); /* no chaining */
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ctx->base.is_jmp = DISAS_NORETURN;
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return true;
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#else
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@ -60,7 +60,7 @@ static bool trans_jalr(DisasContext *ctx, arg_jalr *a)
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if (a->rd != 0) {
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tcg_gen_movi_tl(cpu_gpr[a->rd], ctx->pc_succ_insn);
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}
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tcg_gen_lookup_and_goto_ptr();
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lookup_and_goto_ptr(ctx);
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if (misaligned) {
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gen_set_label(misaligned);
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@ -483,7 +483,7 @@ static bool trans_fence_i(DisasContext *ctx, arg_fence_i *a)
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* however we need to end the translation block
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*/
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tcg_gen_movi_tl(cpu_pc, ctx->pc_succ_insn);
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tcg_gen_exit_tb(NULL, 0);
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exit_tb(ctx);
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ctx->base.is_jmp = DISAS_NORETURN;
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return true;
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}
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@ -504,7 +504,7 @@ static bool trans_fence_i(DisasContext *ctx, arg_fence_i *a)
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gen_io_end(); \
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gen_set_gpr(a->rd, dest); \
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tcg_gen_movi_tl(cpu_pc, ctx->pc_succ_insn); \
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tcg_gen_exit_tb(NULL, 0); \
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exit_tb(ctx); \
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ctx->base.is_jmp = DISAS_NORETURN; \
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tcg_temp_free(source1); \
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tcg_temp_free(csr_store); \
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@ -109,6 +109,26 @@ static void gen_exception_debug(void)
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tcg_temp_free_i32(helper_tmp);
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}
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/* Wrapper around tcg_gen_exit_tb that handles single stepping */
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static void exit_tb(DisasContext *ctx)
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{
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if (ctx->base.singlestep_enabled) {
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gen_exception_debug();
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} else {
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tcg_gen_exit_tb(NULL, 0);
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}
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}
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/* Wrapper around tcg_gen_lookup_and_goto_ptr that handles single stepping */
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static void lookup_and_goto_ptr(DisasContext *ctx)
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{
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if (ctx->base.singlestep_enabled) {
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gen_exception_debug();
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} else {
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tcg_gen_lookup_and_goto_ptr();
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}
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}
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static void gen_exception_illegal(DisasContext *ctx)
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{
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generate_exception(ctx, RISCV_EXCP_ILLEGAL_INST);
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@ -138,14 +158,14 @@ static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
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/* chaining is only allowed when the jump is to the same page */
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tcg_gen_goto_tb(n);
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tcg_gen_movi_tl(cpu_pc, dest);
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/* No need to check for single stepping here as use_goto_tb() will
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* return false in case of single stepping.
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*/
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tcg_gen_exit_tb(ctx->base.tb, n);
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} else {
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tcg_gen_movi_tl(cpu_pc, dest);
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if (ctx->base.singlestep_enabled) {
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gen_exception_debug();
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} else {
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tcg_gen_lookup_and_goto_ptr();
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}
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lookup_and_goto_ptr(ctx);
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}
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}
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