target/i386: move FERR handling to target/i386
Move it out of pc.c since it is strictly tied to TCG. This is almost exclusively code movement, the next patch will implement IGNNE. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
This commit is contained in:
parent
038adc2f58
commit
6f529b7534
17
hw/i386/pc.c
17
hw/i386/pc.c
|
@ -381,23 +381,12 @@ static uint64_t ioport80_read(void *opaque, hwaddr addr, unsigned size)
|
||||||
}
|
}
|
||||||
|
|
||||||
/* MSDOS compatibility mode FPU exception support */
|
/* MSDOS compatibility mode FPU exception support */
|
||||||
static qemu_irq ferr_irq;
|
|
||||||
|
|
||||||
void pc_register_ferr_irq(qemu_irq irq)
|
|
||||||
{
|
|
||||||
ferr_irq = irq;
|
|
||||||
}
|
|
||||||
|
|
||||||
/* XXX: add IGNNE support */
|
|
||||||
void cpu_set_ferr(CPUX86State *s)
|
|
||||||
{
|
|
||||||
qemu_irq_raise(ferr_irq);
|
|
||||||
}
|
|
||||||
|
|
||||||
static void ioportF0_write(void *opaque, hwaddr addr, uint64_t data,
|
static void ioportF0_write(void *opaque, hwaddr addr, uint64_t data,
|
||||||
unsigned size)
|
unsigned size)
|
||||||
{
|
{
|
||||||
qemu_irq_lower(ferr_irq);
|
if (tcg_enabled()) {
|
||||||
|
cpu_clear_ferr();
|
||||||
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
static uint64_t ioportF0_read(void *opaque, hwaddr addr, unsigned size)
|
static uint64_t ioportF0_read(void *opaque, hwaddr addr, unsigned size)
|
||||||
|
|
|
@ -213,7 +213,9 @@ static void pc_init1(MachineState *machine,
|
||||||
ioapic_init_gsi(gsi_state, "i440fx");
|
ioapic_init_gsi(gsi_state, "i440fx");
|
||||||
}
|
}
|
||||||
|
|
||||||
pc_register_ferr_irq(x86ms->gsi[13]);
|
if (tcg_enabled()) {
|
||||||
|
x86_register_ferr_irq(x86ms->gsi[13]);
|
||||||
|
}
|
||||||
|
|
||||||
pc_vga_init(isa_bus, pcmc->pci_enabled ? pci_bus : NULL);
|
pc_vga_init(isa_bus, pcmc->pci_enabled ? pci_bus : NULL);
|
||||||
|
|
||||||
|
|
|
@ -261,7 +261,9 @@ static void pc_q35_init(MachineState *machine)
|
||||||
ioapic_init_gsi(gsi_state, "q35");
|
ioapic_init_gsi(gsi_state, "q35");
|
||||||
}
|
}
|
||||||
|
|
||||||
pc_register_ferr_irq(x86ms->gsi[13]);
|
if (tcg_enabled()) {
|
||||||
|
x86_register_ferr_irq(x86ms->gsi[13]);
|
||||||
|
}
|
||||||
|
|
||||||
assert(pcms->vmport != ON_OFF_AUTO__MAX);
|
assert(pcms->vmport != ON_OFF_AUTO__MAX);
|
||||||
if (pcms->vmport == ON_OFF_AUTO_AUTO) {
|
if (pcms->vmport == ON_OFF_AUTO_AUTO) {
|
||||||
|
|
|
@ -176,7 +176,6 @@ void vmmouse_set_data(const uint32_t *data);
|
||||||
extern int fd_bootchk;
|
extern int fd_bootchk;
|
||||||
|
|
||||||
bool pc_machine_is_smm_enabled(PCMachineState *pcms);
|
bool pc_machine_is_smm_enabled(PCMachineState *pcms);
|
||||||
void pc_register_ferr_irq(qemu_irq irq);
|
|
||||||
void pc_acpi_smi_interrupt(void *opaque, int irq, int level);
|
void pc_acpi_smi_interrupt(void *opaque, int irq, int level);
|
||||||
|
|
||||||
void pc_hot_add_cpu(MachineState *ms, const int64_t id, Error **errp);
|
void pc_hot_add_cpu(MachineState *ms, const int64_t id, Error **errp);
|
||||||
|
|
|
@ -1761,7 +1761,8 @@ int cpu_x86_support_mca_broadcast(CPUX86State *env);
|
||||||
|
|
||||||
int cpu_get_pic_interrupt(CPUX86State *s);
|
int cpu_get_pic_interrupt(CPUX86State *s);
|
||||||
/* MSDOS compatibility mode FPU exception support */
|
/* MSDOS compatibility mode FPU exception support */
|
||||||
void cpu_set_ferr(CPUX86State *s);
|
void x86_register_ferr_irq(qemu_irq irq);
|
||||||
|
void cpu_clear_ferr(void);
|
||||||
/* mpx_helper.c */
|
/* mpx_helper.c */
|
||||||
void cpu_sync_bndcs_hflags(CPUX86State *env);
|
void cpu_sync_bndcs_hflags(CPUX86State *env);
|
||||||
|
|
||||||
|
|
|
@ -26,6 +26,10 @@
|
||||||
#include "exec/cpu_ldst.h"
|
#include "exec/cpu_ldst.h"
|
||||||
#include "fpu/softfloat.h"
|
#include "fpu/softfloat.h"
|
||||||
|
|
||||||
|
#ifdef CONFIG_SOFTMMU
|
||||||
|
#include "hw/irq.h"
|
||||||
|
#endif
|
||||||
|
|
||||||
#define FPU_RC_MASK 0xc00
|
#define FPU_RC_MASK 0xc00
|
||||||
#define FPU_RC_NEAR 0x000
|
#define FPU_RC_NEAR 0x000
|
||||||
#define FPU_RC_DOWN 0x400
|
#define FPU_RC_DOWN 0x400
|
||||||
|
@ -58,6 +62,26 @@
|
||||||
#define floatx80_l2e make_floatx80(0x3fff, 0xb8aa3b295c17f0bcLL)
|
#define floatx80_l2e make_floatx80(0x3fff, 0xb8aa3b295c17f0bcLL)
|
||||||
#define floatx80_l2t make_floatx80(0x4000, 0xd49a784bcd1b8afeLL)
|
#define floatx80_l2t make_floatx80(0x4000, 0xd49a784bcd1b8afeLL)
|
||||||
|
|
||||||
|
#if !defined(CONFIG_USER_ONLY)
|
||||||
|
static qemu_irq ferr_irq;
|
||||||
|
|
||||||
|
void x86_register_ferr_irq(qemu_irq irq)
|
||||||
|
{
|
||||||
|
ferr_irq = irq;
|
||||||
|
}
|
||||||
|
|
||||||
|
void cpu_clear_ferr(void)
|
||||||
|
{
|
||||||
|
qemu_irq_lower(ferr_irq);
|
||||||
|
}
|
||||||
|
|
||||||
|
static void cpu_set_ferr(void)
|
||||||
|
{
|
||||||
|
qemu_irq_raise(ferr_irq);
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
static inline void fpush(CPUX86State *env)
|
static inline void fpush(CPUX86State *env)
|
||||||
{
|
{
|
||||||
env->fpstt = (env->fpstt - 1) & 7;
|
env->fpstt = (env->fpstt - 1) & 7;
|
||||||
|
@ -137,7 +161,7 @@ static void fpu_raise_exception(CPUX86State *env, uintptr_t retaddr)
|
||||||
}
|
}
|
||||||
#if !defined(CONFIG_USER_ONLY)
|
#if !defined(CONFIG_USER_ONLY)
|
||||||
else {
|
else {
|
||||||
cpu_set_ferr(env);
|
cpu_set_ferr();
|
||||||
}
|
}
|
||||||
#endif
|
#endif
|
||||||
}
|
}
|
||||||
|
|
Loading…
Reference in a new issue