Merge branch 'arm-devs.for-upstream' of git://git.linaro.org/people/pmaydell/qemu-arm
* 'arm-devs.for-upstream' of git://git.linaro.org/people/pmaydell/qemu-arm: Versatile Express: Add modelling of NOR flash Versatile Express: Fix NOR flash 0 address and remove flash alias hw/armv7m_nvic: Correctly register GIC region when setting up NVIC pl190: fix read of VECTADDR
This commit is contained in:
commit
6f8fd2530e
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@ -489,7 +489,8 @@ static int armv7m_nvic_init(SysBusDevice *dev)
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*/
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memory_region_init_alias(&s->gic_iomem_alias, "nvic-gic", &s->gic.iomem,
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0x100, 0xc00);
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memory_region_add_subregion_overlap(&s->container, 0x100, &s->gic.iomem, 1);
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memory_region_add_subregion_overlap(&s->container, 0x100,
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&s->gic_iomem_alias, 1);
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/* Map the whole thing into system memory at the location required
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* by the v7M architecture.
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*/
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18
hw/pl190.c
18
hw/pl190.c
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@ -117,12 +117,18 @@ static uint64_t pl190_read(void *opaque, target_phys_addr_t offset,
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return s->protected;
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case 12: /* VECTADDR */
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/* Read vector address at the start of an ISR. Increases the
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current priority level to that of the current interrupt. */
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for (i = 0; i < s->priority; i++)
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{
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if ((s->level | s->soft_level) & s->prio_mask[i])
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break;
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}
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* current priority level to that of the current interrupt.
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*
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* Since an enabled interrupt X at priority P causes prio_mask[Y]
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* to have bit X set for all Y > P, this loop will stop with
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* i == the priority of the highest priority set interrupt.
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*/
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for (i = 0; i < s->priority; i++) {
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if ((s->level | s->soft_level) & s->prio_mask[i + 1]) {
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break;
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}
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}
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/* Reading this value with no pending interrupts is undefined.
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We return the default address. */
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if (i == PL190_NUM_PRIO)
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@ -29,8 +29,12 @@
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#include "sysemu.h"
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#include "boards.h"
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#include "exec-memory.h"
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#include "blockdev.h"
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#include "flash.h"
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#define VEXPRESS_BOARD_ID 0x8e0
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#define VEXPRESS_FLASH_SIZE (64 * 1024 * 1024)
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#define VEXPRESS_FLASH_SECT_SIZE (256 * 1024)
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static struct arm_boot_info vexpress_binfo;
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@ -62,7 +66,6 @@ enum {
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VE_COMPACTFLASH,
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VE_CLCD,
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VE_NORFLASH0,
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VE_NORFLASH0ALIAS,
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VE_NORFLASH1,
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VE_SRAM,
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VE_VIDEORAM,
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@ -104,9 +107,8 @@ static target_phys_addr_t motherboard_legacy_map[] = {
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};
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static target_phys_addr_t motherboard_aseries_map[] = {
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/* CS0: 0x00000000 .. 0x0c000000 */
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[VE_NORFLASH0] = 0x00000000,
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[VE_NORFLASH0ALIAS] = 0x08000000,
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/* CS0: 0x08000000 .. 0x0c000000 */
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[VE_NORFLASH0] = 0x08000000,
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/* CS4: 0x0c000000 .. 0x10000000 */
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[VE_NORFLASH1] = 0x0c000000,
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/* CS5: 0x10000000 .. 0x14000000 */
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@ -357,6 +359,7 @@ static void vexpress_common_init(const VEDBoardInfo *daughterboard,
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qemu_irq pic[64];
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uint32_t proc_id;
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uint32_t sys_id;
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DriveInfo *dinfo;
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ram_addr_t vram_size, sram_size;
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MemoryRegion *sysmem = get_system_memory();
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MemoryRegion *vram = g_new(MemoryRegion, 1);
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@ -412,9 +415,25 @@ static void vexpress_common_init(const VEDBoardInfo *daughterboard,
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sysbus_create_simple("pl111", map[VE_CLCD], pic[14]);
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/* VE_NORFLASH0: not modelled */
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/* VE_NORFLASH0ALIAS: not modelled */
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/* VE_NORFLASH1: not modelled */
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dinfo = drive_get_next(IF_PFLASH);
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if (!pflash_cfi01_register(map[VE_NORFLASH0], NULL, "vexpress.flash0",
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VEXPRESS_FLASH_SIZE, dinfo ? dinfo->bdrv : NULL,
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VEXPRESS_FLASH_SECT_SIZE,
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VEXPRESS_FLASH_SIZE / VEXPRESS_FLASH_SECT_SIZE, 4,
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0x00, 0x89, 0x00, 0x18, 0)) {
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fprintf(stderr, "vexpress: error registering flash 0.\n");
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exit(1);
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}
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dinfo = drive_get_next(IF_PFLASH);
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if (!pflash_cfi01_register(map[VE_NORFLASH1], NULL, "vexpress.flash1",
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VEXPRESS_FLASH_SIZE, dinfo ? dinfo->bdrv : NULL,
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VEXPRESS_FLASH_SECT_SIZE,
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VEXPRESS_FLASH_SIZE / VEXPRESS_FLASH_SECT_SIZE, 4,
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0x00, 0x89, 0x00, 0x18, 0)) {
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fprintf(stderr, "vexpress: error registering flash 1.\n");
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exit(1);
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}
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sram_size = 0x2000000;
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memory_region_init_ram(sram, "vexpress.sram", sram_size);
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