introduce aux-bus
This introduces a new bus: aux-bus. It contains an address space for aux slaves devices and a bridge to an I2C bus for I2C through AUX transactions. Signed-off-by: KONRAD Frederic <fred.konrad@greensocs.com> Tested-By: Hyun Kwon <hyun.kwon@xilinx.com> Reviewed-by: Alistair Francis <alistair.francis@xilinx.com> Message-id: 1465833014-21982-5-git-send-email-fred.konrad@greensocs.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
parent
056fca7b51
commit
6fc7f77fd2
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@ -3,4 +3,5 @@
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# We support all the 32 bit boards so need all their config
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# We support all the 32 bit boards so need all their config
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include arm-softmmu.mak
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include arm-softmmu.mak
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CONFIG_AUX=y
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CONFIG_XLNX_ZYNQMP=y
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CONFIG_XLNX_ZYNQMP=y
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@ -51,3 +51,4 @@ obj-$(CONFIG_MIPS_ITU) += mips_itu.o
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obj-$(CONFIG_PVPANIC) += pvpanic.o
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obj-$(CONFIG_PVPANIC) += pvpanic.o
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obj-$(CONFIG_EDU) += edu.o
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obj-$(CONFIG_EDU) += edu.o
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obj-$(CONFIG_HYPERV_TESTDEV) += hyperv_testdev.o
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obj-$(CONFIG_HYPERV_TESTDEV) += hyperv_testdev.o
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obj-$(CONFIG_AUX) += aux.o
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292
hw/misc/aux.c
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292
hw/misc/aux.c
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@ -0,0 +1,292 @@
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/*
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* aux.c
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*
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* Copyright 2015 : GreenSocs Ltd
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* http://www.greensocs.com/ , email: info@greensocs.com
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*
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* Developed by :
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* Frederic Konrad <fred.konrad@greensocs.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 2 of the License, or
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* (at your option)any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, see <http://www.gnu.org/licenses/>.
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*
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*/
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/*
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* This is an implementation of the AUX bus for VESA Display Port v1.1a.
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*/
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#include "qemu/osdep.h"
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#include "qemu/log.h"
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#include "hw/misc/aux.h"
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#include "hw/i2c/i2c.h"
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#include "monitor/monitor.h"
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#ifndef DEBUG_AUX
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#define DEBUG_AUX 0
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#endif
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#define DPRINTF(fmt, ...) do { \
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if (DEBUG_AUX) { \
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qemu_log("aux: " fmt , ## __VA_ARGS__); \
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} \
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} while (0);
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#define TYPE_AUXTOI2C "aux-to-i2c-bridge"
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#define AUXTOI2C(obj) OBJECT_CHECK(AUXTOI2CState, (obj), TYPE_AUXTOI2C)
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static void aux_slave_dev_print(Monitor *mon, DeviceState *dev, int indent);
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static inline I2CBus *aux_bridge_get_i2c_bus(AUXTOI2CState *bridge);
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/* aux-bus implementation (internal not public) */
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static void aux_bus_class_init(ObjectClass *klass, void *data)
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{
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BusClass *k = BUS_CLASS(klass);
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/* AUXSlave has an MMIO so we need to change the way we print information
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* in monitor.
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*/
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k->print_dev = aux_slave_dev_print;
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}
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AUXBus *aux_init_bus(DeviceState *parent, const char *name)
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{
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AUXBus *bus;
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bus = AUX_BUS(qbus_create(TYPE_AUX_BUS, parent, name));
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bus->bridge = AUXTOI2C(qdev_create(BUS(bus), TYPE_AUXTOI2C));
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/* Memory related. */
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bus->aux_io = g_malloc(sizeof(*bus->aux_io));
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memory_region_init(bus->aux_io, OBJECT(bus), "aux-io", (1 << 20));
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address_space_init(&bus->aux_addr_space, bus->aux_io, "aux-io");
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return bus;
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}
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static void aux_bus_map_device(AUXBus *bus, AUXSlave *dev, hwaddr addr)
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{
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memory_region_add_subregion(bus->aux_io, addr, dev->mmio);
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}
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static bool aux_bus_is_bridge(AUXBus *bus, DeviceState *dev)
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{
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return (dev == DEVICE(bus->bridge));
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}
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I2CBus *aux_get_i2c_bus(AUXBus *bus)
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{
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return aux_bridge_get_i2c_bus(bus->bridge);
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}
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AUXReply aux_request(AUXBus *bus, AUXCommand cmd, uint32_t address,
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uint8_t len, uint8_t *data)
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{
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AUXReply ret = AUX_NACK;
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I2CBus *i2c_bus = aux_get_i2c_bus(bus);
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size_t i;
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bool is_write = false;
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DPRINTF("request at address 0x%" PRIX32 ", command %u, len %u\n", address,
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cmd, len);
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switch (cmd) {
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/*
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* Forward the request on the AUX bus..
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*/
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case WRITE_AUX:
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case READ_AUX:
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is_write = cmd == READ_AUX ? false : true;
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for (i = 0; i < len; i++) {
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if (!address_space_rw(&bus->aux_addr_space, address++,
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MEMTXATTRS_UNSPECIFIED, data++, 1,
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is_write)) {
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ret = AUX_I2C_ACK;
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} else {
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ret = AUX_NACK;
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break;
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}
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}
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break;
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/*
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* Classic I2C transactions..
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*/
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case READ_I2C:
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case WRITE_I2C:
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is_write = cmd == READ_I2C ? false : true;
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if (i2c_bus_busy(i2c_bus)) {
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i2c_end_transfer(i2c_bus);
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}
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if (i2c_start_transfer(i2c_bus, address, is_write)) {
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ret = AUX_I2C_NACK;
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break;
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}
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ret = AUX_I2C_ACK;
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while (len > 0) {
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if (i2c_send_recv(i2c_bus, data++, is_write) < 0) {
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ret = AUX_I2C_NACK;
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break;
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}
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len--;
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}
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i2c_end_transfer(i2c_bus);
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break;
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/*
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* I2C MOT transactions.
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*
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* Here we send a start when:
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* - We didn't start transaction yet.
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* - We had a READ and we do a WRITE.
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* - We changed the address.
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*/
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case WRITE_I2C_MOT:
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case READ_I2C_MOT:
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is_write = cmd == READ_I2C_MOT ? false : true;
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if (!i2c_bus_busy(i2c_bus)) {
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/*
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* No transactions started..
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*/
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if (i2c_start_transfer(i2c_bus, address, is_write)) {
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ret = AUX_I2C_NACK;
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break;
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}
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} else if ((address != bus->last_i2c_address) ||
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(bus->last_transaction != cmd)) {
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/*
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* Transaction started but we need to restart..
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*/
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i2c_end_transfer(i2c_bus);
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if (i2c_start_transfer(i2c_bus, address, is_write)) {
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ret = AUX_I2C_NACK;
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break;
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}
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}
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while (len > 0) {
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if (i2c_send_recv(i2c_bus, data++, is_write) < 0) {
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ret = AUX_I2C_NACK;
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i2c_end_transfer(i2c_bus);
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break;
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}
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len--;
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}
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bus->last_transaction = cmd;
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bus->last_i2c_address = address;
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ret = AUX_I2C_ACK;
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break;
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default:
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DPRINTF("Not implemented!\n");
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return AUX_NACK;
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}
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DPRINTF("reply: %u\n", ret);
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return ret;
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}
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static const TypeInfo aux_bus_info = {
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.name = TYPE_AUX_BUS,
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.parent = TYPE_BUS,
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.instance_size = sizeof(AUXBus),
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.class_init = aux_bus_class_init
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};
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/* aux-i2c implementation (internal not public) */
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struct AUXTOI2CState {
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/*< private >*/
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DeviceState parent_obj;
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/*< public >*/
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I2CBus *i2c_bus;
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};
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static void aux_bridge_init(Object *obj)
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{
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AUXTOI2CState *s = AUXTOI2C(obj);
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s->i2c_bus = i2c_init_bus(DEVICE(obj), "aux-i2c");
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}
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static inline I2CBus *aux_bridge_get_i2c_bus(AUXTOI2CState *bridge)
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{
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return bridge->i2c_bus;
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}
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static const TypeInfo aux_to_i2c_type_info = {
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.name = TYPE_AUXTOI2C,
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.parent = TYPE_DEVICE,
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.instance_size = sizeof(AUXTOI2CState),
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.instance_init = aux_bridge_init
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};
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/* aux-slave implementation */
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static void aux_slave_dev_print(Monitor *mon, DeviceState *dev, int indent)
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{
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AUXBus *bus = AUX_BUS(qdev_get_parent_bus(dev));
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AUXSlave *s;
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/* Don't print anything if the device is I2C "bridge". */
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if (aux_bus_is_bridge(bus, dev)) {
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return;
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}
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s = AUX_SLAVE(dev);
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monitor_printf(mon, "%*smemory " TARGET_FMT_plx "/" TARGET_FMT_plx "\n",
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indent, "",
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object_property_get_int(OBJECT(s->mmio), "addr", NULL),
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memory_region_size(s->mmio));
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}
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DeviceState *aux_create_slave(AUXBus *bus, const char *type, uint32_t addr)
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{
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DeviceState *dev;
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dev = DEVICE(object_new(type));
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assert(dev);
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qdev_set_parent_bus(dev, &bus->qbus);
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qdev_init_nofail(dev);
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aux_bus_map_device(AUX_BUS(qdev_get_parent_bus(dev)), AUX_SLAVE(dev), addr);
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return dev;
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}
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void aux_init_mmio(AUXSlave *aux_slave, MemoryRegion *mmio)
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{
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assert(!aux_slave->mmio);
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aux_slave->mmio = mmio;
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}
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static void aux_slave_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *k = DEVICE_CLASS(klass);
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set_bit(DEVICE_CATEGORY_MISC, k->categories);
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k->bus_type = TYPE_AUX_BUS;
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}
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static const TypeInfo aux_slave_type_info = {
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.name = TYPE_AUX_SLAVE,
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.parent = TYPE_DEVICE,
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.instance_size = sizeof(AUXSlave),
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.abstract = true,
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.class_init = aux_slave_class_init,
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};
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static void aux_register_types(void)
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{
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type_register_static(&aux_bus_info);
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type_register_static(&aux_slave_type_info);
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type_register_static(&aux_to_i2c_type_info);
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}
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type_init(aux_register_types)
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128
include/hw/misc/aux.h
Normal file
128
include/hw/misc/aux.h
Normal file
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@ -0,0 +1,128 @@
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/*
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* aux.h
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*
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* Copyright (C)2014 : GreenSocs Ltd
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* http://www.greensocs.com/ , email: info@greensocs.com
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*
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* Developed by :
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* Frederic Konrad <fred.konrad@greensocs.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
|
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* the Free Software Foundation, either version 2 of the License, or
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* (at your option)any later version.
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*
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|
* This program is distributed in the hope that it will be useful,
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||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
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|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
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|
* GNU General Public License for more details.
|
||||||
|
*
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|
* You should have received a copy of the GNU General Public License along
|
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* with this program; if not, see <http://www.gnu.org/licenses/>.
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*
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*/
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#ifndef QEMU_AUX_H
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#define QEMU_AUX_H
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#include "hw/qdev.h"
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typedef struct AUXBus AUXBus;
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typedef struct AUXSlave AUXSlave;
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typedef enum AUXCommand AUXCommand;
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typedef enum AUXReply AUXReply;
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typedef struct AUXTOI2CState AUXTOI2CState;
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enum AUXCommand {
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WRITE_I2C = 0,
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READ_I2C = 1,
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WRITE_I2C_STATUS = 2,
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WRITE_I2C_MOT = 4,
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READ_I2C_MOT = 5,
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WRITE_AUX = 8,
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READ_AUX = 9
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};
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enum AUXReply {
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AUX_I2C_ACK = 0,
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AUX_NACK = 1,
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AUX_DEFER = 2,
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AUX_I2C_NACK = 4,
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AUX_I2C_DEFER = 8
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};
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#define TYPE_AUX_BUS "aux-bus"
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#define AUX_BUS(obj) OBJECT_CHECK(AUXBus, (obj), TYPE_AUX_BUS)
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struct AUXBus {
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/* < private > */
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BusState qbus;
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/* < public > */
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AUXSlave *current_dev;
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AUXSlave *dev;
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uint32_t last_i2c_address;
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AUXCommand last_transaction;
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AUXTOI2CState *bridge;
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MemoryRegion *aux_io;
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AddressSpace aux_addr_space;
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};
|
||||||
|
|
||||||
|
#define TYPE_AUX_SLAVE "aux-slave"
|
||||||
|
#define AUX_SLAVE(obj) \
|
||||||
|
OBJECT_CHECK(AUXSlave, (obj), TYPE_AUX_SLAVE)
|
||||||
|
|
||||||
|
struct AUXSlave {
|
||||||
|
/* < private > */
|
||||||
|
DeviceState parent_obj;
|
||||||
|
|
||||||
|
/* < public > */
|
||||||
|
MemoryRegion *mmio;
|
||||||
|
};
|
||||||
|
|
||||||
|
/**
|
||||||
|
* aux_init_bus: Initialize an AUX bus.
|
||||||
|
*
|
||||||
|
* Returns the new AUX bus created.
|
||||||
|
*
|
||||||
|
* @parent The device where this bus is located.
|
||||||
|
* @name The name of the bus.
|
||||||
|
*/
|
||||||
|
AUXBus *aux_init_bus(DeviceState *parent, const char *name);
|
||||||
|
|
||||||
|
/*
|
||||||
|
* aux_request: Make a request on the bus.
|
||||||
|
*
|
||||||
|
* Returns the reply of the request.
|
||||||
|
*
|
||||||
|
* @bus Ths bus where the request happen.
|
||||||
|
* @cmd The command requested.
|
||||||
|
* @address The 20bits address of the slave.
|
||||||
|
* @len The length of the read or write.
|
||||||
|
* @data The data array which will be filled or read during transfer.
|
||||||
|
*/
|
||||||
|
AUXReply aux_request(AUXBus *bus, AUXCommand cmd, uint32_t address,
|
||||||
|
uint8_t len, uint8_t *data);
|
||||||
|
|
||||||
|
/*
|
||||||
|
* aux_get_i2c_bus: Get the i2c bus for I2C over AUX command.
|
||||||
|
*
|
||||||
|
* Returns the i2c bus associated to this AUX bus.
|
||||||
|
*
|
||||||
|
* @bus The AUX bus.
|
||||||
|
*/
|
||||||
|
I2CBus *aux_get_i2c_bus(AUXBus *bus);
|
||||||
|
|
||||||
|
/*
|
||||||
|
* aux_init_mmio: Init an mmio for an AUX slave.
|
||||||
|
*
|
||||||
|
* @aux_slave The AUX slave.
|
||||||
|
* @mmio The mmio to be registered.
|
||||||
|
*/
|
||||||
|
void aux_init_mmio(AUXSlave *aux_slave, MemoryRegion *mmio);
|
||||||
|
|
||||||
|
DeviceState *aux_create_slave(AUXBus *bus, const char *name, uint32_t addr);
|
||||||
|
|
||||||
|
#endif /* !QEMU_AUX_H */
|
Loading…
Reference in a new issue