ppc: Pass PowerPCCPU to ppc_set_irq()
Adapt static caller functions. This cleans up after passing PowerPCCPU to kvmppc_set_interrupt(). Signed-off-by: Andreas Färber <afaerber@suse.de>
This commit is contained in:
parent
1bc22652d6
commit
7058581a26
66
hw/ppc.c
66
hw/ppc.c
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@ -50,8 +50,9 @@
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static void cpu_ppc_tb_stop (CPUPPCState *env);
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static void cpu_ppc_tb_stop (CPUPPCState *env);
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static void cpu_ppc_tb_start (CPUPPCState *env);
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static void cpu_ppc_tb_start (CPUPPCState *env);
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void ppc_set_irq(CPUPPCState *env, int n_IRQ, int level)
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void ppc_set_irq(PowerPCCPU *cpu, int n_IRQ, int level)
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{
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{
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CPUPPCState *env = &cpu->env;
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unsigned int old_pending = env->pending_interrupts;
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unsigned int old_pending = env->pending_interrupts;
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if (level) {
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if (level) {
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@ -65,7 +66,7 @@ void ppc_set_irq(CPUPPCState *env, int n_IRQ, int level)
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if (old_pending != env->pending_interrupts) {
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if (old_pending != env->pending_interrupts) {
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#ifdef CONFIG_KVM
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#ifdef CONFIG_KVM
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kvmppc_set_interrupt(ppc_env_get_cpu(env), n_IRQ, level);
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kvmppc_set_interrupt(cpu, n_IRQ, level);
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#endif
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#endif
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}
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}
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@ -100,13 +101,13 @@ static void ppc6xx_set_irq(void *opaque, int pin, int level)
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/* Level sensitive - active high */
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/* Level sensitive - active high */
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LOG_IRQ("%s: set the external IRQ state to %d\n",
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LOG_IRQ("%s: set the external IRQ state to %d\n",
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__func__, level);
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__func__, level);
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ppc_set_irq(env, PPC_INTERRUPT_EXT, level);
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ppc_set_irq(cpu, PPC_INTERRUPT_EXT, level);
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break;
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break;
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case PPC6xx_INPUT_SMI:
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case PPC6xx_INPUT_SMI:
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/* Level sensitive - active high */
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/* Level sensitive - active high */
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LOG_IRQ("%s: set the SMI IRQ state to %d\n",
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LOG_IRQ("%s: set the SMI IRQ state to %d\n",
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__func__, level);
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__func__, level);
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ppc_set_irq(env, PPC_INTERRUPT_SMI, level);
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ppc_set_irq(cpu, PPC_INTERRUPT_SMI, level);
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break;
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break;
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case PPC6xx_INPUT_MCP:
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case PPC6xx_INPUT_MCP:
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/* Negative edge sensitive */
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/* Negative edge sensitive */
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@ -116,7 +117,7 @@ static void ppc6xx_set_irq(void *opaque, int pin, int level)
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if (cur_level == 1 && level == 0) {
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if (cur_level == 1 && level == 0) {
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LOG_IRQ("%s: raise machine check state\n",
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LOG_IRQ("%s: raise machine check state\n",
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__func__);
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__func__);
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ppc_set_irq(env, PPC_INTERRUPT_MCK, 1);
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ppc_set_irq(cpu, PPC_INTERRUPT_MCK, 1);
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}
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}
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break;
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break;
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case PPC6xx_INPUT_CKSTP_IN:
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case PPC6xx_INPUT_CKSTP_IN:
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@ -138,7 +139,7 @@ static void ppc6xx_set_irq(void *opaque, int pin, int level)
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case PPC6xx_INPUT_SRESET:
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case PPC6xx_INPUT_SRESET:
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LOG_IRQ("%s: set the RESET IRQ state to %d\n",
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LOG_IRQ("%s: set the RESET IRQ state to %d\n",
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__func__, level);
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__func__, level);
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ppc_set_irq(env, PPC_INTERRUPT_RESET, level);
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ppc_set_irq(cpu, PPC_INTERRUPT_RESET, level);
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break;
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break;
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default:
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default:
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/* Unknown pin - do nothing */
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/* Unknown pin - do nothing */
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@ -178,13 +179,13 @@ static void ppc970_set_irq(void *opaque, int pin, int level)
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/* Level sensitive - active high */
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/* Level sensitive - active high */
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LOG_IRQ("%s: set the external IRQ state to %d\n",
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LOG_IRQ("%s: set the external IRQ state to %d\n",
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__func__, level);
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__func__, level);
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ppc_set_irq(env, PPC_INTERRUPT_EXT, level);
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ppc_set_irq(cpu, PPC_INTERRUPT_EXT, level);
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break;
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break;
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case PPC970_INPUT_THINT:
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case PPC970_INPUT_THINT:
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/* Level sensitive - active high */
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/* Level sensitive - active high */
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LOG_IRQ("%s: set the SMI IRQ state to %d\n", __func__,
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LOG_IRQ("%s: set the SMI IRQ state to %d\n", __func__,
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level);
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level);
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ppc_set_irq(env, PPC_INTERRUPT_THERM, level);
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ppc_set_irq(cpu, PPC_INTERRUPT_THERM, level);
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break;
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break;
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case PPC970_INPUT_MCP:
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case PPC970_INPUT_MCP:
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/* Negative edge sensitive */
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/* Negative edge sensitive */
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@ -194,7 +195,7 @@ static void ppc970_set_irq(void *opaque, int pin, int level)
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if (cur_level == 1 && level == 0) {
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if (cur_level == 1 && level == 0) {
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LOG_IRQ("%s: raise machine check state\n",
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LOG_IRQ("%s: raise machine check state\n",
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__func__);
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__func__);
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ppc_set_irq(env, PPC_INTERRUPT_MCK, 1);
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ppc_set_irq(cpu, PPC_INTERRUPT_MCK, 1);
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}
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}
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break;
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break;
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case PPC970_INPUT_CKSTP:
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case PPC970_INPUT_CKSTP:
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@ -218,7 +219,7 @@ static void ppc970_set_irq(void *opaque, int pin, int level)
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case PPC970_INPUT_SRESET:
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case PPC970_INPUT_SRESET:
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LOG_IRQ("%s: set the RESET IRQ state to %d\n",
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LOG_IRQ("%s: set the RESET IRQ state to %d\n",
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__func__, level);
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__func__, level);
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ppc_set_irq(env, PPC_INTERRUPT_RESET, level);
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ppc_set_irq(cpu, PPC_INTERRUPT_RESET, level);
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break;
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break;
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case PPC970_INPUT_TBEN:
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case PPC970_INPUT_TBEN:
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LOG_IRQ("%s: set the TBEN state to %d\n", __func__,
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LOG_IRQ("%s: set the TBEN state to %d\n", __func__,
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@ -259,7 +260,7 @@ static void power7_set_irq(void *opaque, int pin, int level)
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/* Level sensitive - active high */
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/* Level sensitive - active high */
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LOG_IRQ("%s: set the external IRQ state to %d\n",
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LOG_IRQ("%s: set the external IRQ state to %d\n",
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__func__, level);
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__func__, level);
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ppc_set_irq(env, PPC_INTERRUPT_EXT, level);
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ppc_set_irq(cpu, PPC_INTERRUPT_EXT, level);
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break;
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break;
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default:
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default:
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/* Unknown pin - do nothing */
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/* Unknown pin - do nothing */
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@ -319,13 +320,13 @@ static void ppc40x_set_irq(void *opaque, int pin, int level)
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/* Level sensitive - active high */
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/* Level sensitive - active high */
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LOG_IRQ("%s: set the critical IRQ state to %d\n",
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LOG_IRQ("%s: set the critical IRQ state to %d\n",
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__func__, level);
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__func__, level);
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ppc_set_irq(env, PPC_INTERRUPT_CEXT, level);
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ppc_set_irq(cpu, PPC_INTERRUPT_CEXT, level);
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break;
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break;
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case PPC40x_INPUT_INT:
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case PPC40x_INPUT_INT:
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/* Level sensitive - active high */
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/* Level sensitive - active high */
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LOG_IRQ("%s: set the external IRQ state to %d\n",
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LOG_IRQ("%s: set the external IRQ state to %d\n",
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__func__, level);
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__func__, level);
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ppc_set_irq(env, PPC_INTERRUPT_EXT, level);
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ppc_set_irq(cpu, PPC_INTERRUPT_EXT, level);
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break;
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break;
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case PPC40x_INPUT_HALT:
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case PPC40x_INPUT_HALT:
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/* Level sensitive - active low */
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/* Level sensitive - active low */
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@ -342,7 +343,7 @@ static void ppc40x_set_irq(void *opaque, int pin, int level)
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/* Level sensitive - active high */
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/* Level sensitive - active high */
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LOG_IRQ("%s: set the debug pin state to %d\n",
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LOG_IRQ("%s: set the debug pin state to %d\n",
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__func__, level);
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__func__, level);
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ppc_set_irq(env, PPC_INTERRUPT_DEBUG, level);
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ppc_set_irq(cpu, PPC_INTERRUPT_DEBUG, level);
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break;
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break;
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default:
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default:
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/* Unknown pin - do nothing */
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/* Unknown pin - do nothing */
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@ -387,26 +388,26 @@ static void ppce500_set_irq(void *opaque, int pin, int level)
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case PPCE500_INPUT_RESET_CORE:
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case PPCE500_INPUT_RESET_CORE:
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if (level) {
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if (level) {
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LOG_IRQ("%s: reset the PowerPC core\n", __func__);
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LOG_IRQ("%s: reset the PowerPC core\n", __func__);
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ppc_set_irq(env, PPC_INTERRUPT_MCK, level);
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ppc_set_irq(cpu, PPC_INTERRUPT_MCK, level);
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}
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}
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break;
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break;
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case PPCE500_INPUT_CINT:
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case PPCE500_INPUT_CINT:
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/* Level sensitive - active high */
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/* Level sensitive - active high */
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LOG_IRQ("%s: set the critical IRQ state to %d\n",
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LOG_IRQ("%s: set the critical IRQ state to %d\n",
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__func__, level);
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__func__, level);
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ppc_set_irq(env, PPC_INTERRUPT_CEXT, level);
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ppc_set_irq(cpu, PPC_INTERRUPT_CEXT, level);
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break;
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break;
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case PPCE500_INPUT_INT:
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case PPCE500_INPUT_INT:
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/* Level sensitive - active high */
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/* Level sensitive - active high */
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LOG_IRQ("%s: set the core IRQ state to %d\n",
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LOG_IRQ("%s: set the core IRQ state to %d\n",
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__func__, level);
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__func__, level);
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ppc_set_irq(env, PPC_INTERRUPT_EXT, level);
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ppc_set_irq(cpu, PPC_INTERRUPT_EXT, level);
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break;
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break;
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case PPCE500_INPUT_DEBUG:
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case PPCE500_INPUT_DEBUG:
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/* Level sensitive - active high */
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/* Level sensitive - active high */
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LOG_IRQ("%s: set the debug pin state to %d\n",
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LOG_IRQ("%s: set the debug pin state to %d\n",
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__func__, level);
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__func__, level);
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ppc_set_irq(env, PPC_INTERRUPT_DEBUG, level);
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ppc_set_irq(cpu, PPC_INTERRUPT_DEBUG, level);
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break;
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break;
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default:
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default:
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/* Unknown pin - do nothing */
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/* Unknown pin - do nothing */
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@ -645,16 +646,20 @@ uint64_t cpu_ppc_load_purr (CPUPPCState *env)
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*/
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*/
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static inline void cpu_ppc_decr_excp(CPUPPCState *env)
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static inline void cpu_ppc_decr_excp(CPUPPCState *env)
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{
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{
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PowerPCCPU *cpu = ppc_env_get_cpu(env);
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/* Raise it */
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/* Raise it */
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LOG_TB("raise decrementer exception\n");
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LOG_TB("raise decrementer exception\n");
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ppc_set_irq(env, PPC_INTERRUPT_DECR, 1);
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ppc_set_irq(cpu, PPC_INTERRUPT_DECR, 1);
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}
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}
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static inline void cpu_ppc_hdecr_excp(CPUPPCState *env)
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static inline void cpu_ppc_hdecr_excp(CPUPPCState *env)
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{
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{
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PowerPCCPU *cpu = ppc_env_get_cpu(env);
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/* Raise it */
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/* Raise it */
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LOG_TB("raise decrementer exception\n");
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LOG_TB("raise decrementer exception\n");
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ppc_set_irq(env, PPC_INTERRUPT_HDECR, 1);
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ppc_set_irq(cpu, PPC_INTERRUPT_HDECR, 1);
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}
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}
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static void __cpu_ppc_store_decr (CPUPPCState *env, uint64_t *nextp,
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static void __cpu_ppc_store_decr (CPUPPCState *env, uint64_t *nextp,
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@ -829,12 +834,14 @@ struct ppc40x_timer_t {
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/* Fixed interval timer */
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/* Fixed interval timer */
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static void cpu_4xx_fit_cb (void *opaque)
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static void cpu_4xx_fit_cb (void *opaque)
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{
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{
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PowerPCCPU *cpu;
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CPUPPCState *env;
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CPUPPCState *env;
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ppc_tb_t *tb_env;
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ppc_tb_t *tb_env;
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ppc40x_timer_t *ppc40x_timer;
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ppc40x_timer_t *ppc40x_timer;
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uint64_t now, next;
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uint64_t now, next;
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env = opaque;
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env = opaque;
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cpu = ppc_env_get_cpu(env);
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tb_env = env->tb_env;
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tb_env = env->tb_env;
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ppc40x_timer = tb_env->opaque;
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ppc40x_timer = tb_env->opaque;
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now = qemu_get_clock_ns(vm_clock);
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now = qemu_get_clock_ns(vm_clock);
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@ -860,8 +867,9 @@ static void cpu_4xx_fit_cb (void *opaque)
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next++;
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next++;
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qemu_mod_timer(ppc40x_timer->fit_timer, next);
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qemu_mod_timer(ppc40x_timer->fit_timer, next);
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env->spr[SPR_40x_TSR] |= 1 << 26;
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env->spr[SPR_40x_TSR] |= 1 << 26;
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if ((env->spr[SPR_40x_TCR] >> 23) & 0x1)
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if ((env->spr[SPR_40x_TCR] >> 23) & 0x1) {
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ppc_set_irq(env, PPC_INTERRUPT_FIT, 1);
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ppc_set_irq(cpu, PPC_INTERRUPT_FIT, 1);
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}
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LOG_TB("%s: ir %d TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx "\n", __func__,
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LOG_TB("%s: ir %d TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx "\n", __func__,
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(int)((env->spr[SPR_40x_TCR] >> 23) & 0x1),
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(int)((env->spr[SPR_40x_TCR] >> 23) & 0x1),
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env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR]);
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env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR]);
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@ -897,16 +905,19 @@ static void start_stop_pit (CPUPPCState *env, ppc_tb_t *tb_env, int is_excp)
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static void cpu_4xx_pit_cb (void *opaque)
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static void cpu_4xx_pit_cb (void *opaque)
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{
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{
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PowerPCCPU *cpu;
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CPUPPCState *env;
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CPUPPCState *env;
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ppc_tb_t *tb_env;
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ppc_tb_t *tb_env;
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ppc40x_timer_t *ppc40x_timer;
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ppc40x_timer_t *ppc40x_timer;
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env = opaque;
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env = opaque;
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cpu = ppc_env_get_cpu(env);
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tb_env = env->tb_env;
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tb_env = env->tb_env;
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ppc40x_timer = tb_env->opaque;
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ppc40x_timer = tb_env->opaque;
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env->spr[SPR_40x_TSR] |= 1 << 27;
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env->spr[SPR_40x_TSR] |= 1 << 27;
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if ((env->spr[SPR_40x_TCR] >> 26) & 0x1)
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if ((env->spr[SPR_40x_TCR] >> 26) & 0x1) {
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ppc_set_irq(env, ppc40x_timer->decr_excp, 1);
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ppc_set_irq(cpu, ppc40x_timer->decr_excp, 1);
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}
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start_stop_pit(env, tb_env, 1);
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start_stop_pit(env, tb_env, 1);
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LOG_TB("%s: ar %d ir %d TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx " "
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LOG_TB("%s: ar %d ir %d TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx " "
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"%016" PRIx64 "\n", __func__,
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"%016" PRIx64 "\n", __func__,
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@ -919,12 +930,14 @@ static void cpu_4xx_pit_cb (void *opaque)
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/* Watchdog timer */
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/* Watchdog timer */
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static void cpu_4xx_wdt_cb (void *opaque)
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static void cpu_4xx_wdt_cb (void *opaque)
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{
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{
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PowerPCCPU *cpu;
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CPUPPCState *env;
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CPUPPCState *env;
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ppc_tb_t *tb_env;
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ppc_tb_t *tb_env;
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ppc40x_timer_t *ppc40x_timer;
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ppc40x_timer_t *ppc40x_timer;
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uint64_t now, next;
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uint64_t now, next;
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env = opaque;
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env = opaque;
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cpu = ppc_env_get_cpu(env);
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tb_env = env->tb_env;
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tb_env = env->tb_env;
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ppc40x_timer = tb_env->opaque;
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ppc40x_timer = tb_env->opaque;
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now = qemu_get_clock_ns(vm_clock);
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now = qemu_get_clock_ns(vm_clock);
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@ -961,8 +974,9 @@ static void cpu_4xx_wdt_cb (void *opaque)
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qemu_mod_timer(ppc40x_timer->wdt_timer, next);
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qemu_mod_timer(ppc40x_timer->wdt_timer, next);
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ppc40x_timer->wdt_next = next;
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ppc40x_timer->wdt_next = next;
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env->spr[SPR_40x_TSR] |= 1 << 30;
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env->spr[SPR_40x_TSR] |= 1 << 30;
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if ((env->spr[SPR_40x_TCR] >> 27) & 0x1)
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if ((env->spr[SPR_40x_TCR] >> 27) & 0x1) {
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ppc_set_irq(env, PPC_INTERRUPT_WDT, 1);
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ppc_set_irq(cpu, PPC_INTERRUPT_WDT, 1);
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}
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break;
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break;
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case 0x3:
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case 0x3:
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env->spr[SPR_40x_TSR] &= ~0x30000000;
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env->spr[SPR_40x_TSR] &= ~0x30000000;
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2
hw/ppc.h
2
hw/ppc.h
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@ -1,4 +1,4 @@
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void ppc_set_irq (CPUPPCState *env, int n_IRQ, int level);
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void ppc_set_irq(PowerPCCPU *cpu, int n_IRQ, int level);
|
||||||
|
|
||||||
/* PowerPC hardware exceptions management helpers */
|
/* PowerPC hardware exceptions management helpers */
|
||||||
typedef void (*clk_setup_cb)(void *opaque, uint32_t freq);
|
typedef void (*clk_setup_cb)(void *opaque, uint32_t freq);
|
||||||
|
|
|
@ -71,17 +71,19 @@ struct booke_timer_t {
|
||||||
uint32_t flags;
|
uint32_t flags;
|
||||||
};
|
};
|
||||||
|
|
||||||
static void booke_update_irq(CPUPPCState *env)
|
static void booke_update_irq(PowerPCCPU *cpu)
|
||||||
{
|
{
|
||||||
ppc_set_irq(env, PPC_INTERRUPT_DECR,
|
CPUPPCState *env = &cpu->env;
|
||||||
|
|
||||||
|
ppc_set_irq(cpu, PPC_INTERRUPT_DECR,
|
||||||
(env->spr[SPR_BOOKE_TSR] & TSR_DIS
|
(env->spr[SPR_BOOKE_TSR] & TSR_DIS
|
||||||
&& env->spr[SPR_BOOKE_TCR] & TCR_DIE));
|
&& env->spr[SPR_BOOKE_TCR] & TCR_DIE));
|
||||||
|
|
||||||
ppc_set_irq(env, PPC_INTERRUPT_WDT,
|
ppc_set_irq(cpu, PPC_INTERRUPT_WDT,
|
||||||
(env->spr[SPR_BOOKE_TSR] & TSR_WIS
|
(env->spr[SPR_BOOKE_TSR] & TSR_WIS
|
||||||
&& env->spr[SPR_BOOKE_TCR] & TCR_WIE));
|
&& env->spr[SPR_BOOKE_TCR] & TCR_WIE));
|
||||||
|
|
||||||
ppc_set_irq(env, PPC_INTERRUPT_FIT,
|
ppc_set_irq(cpu, PPC_INTERRUPT_FIT,
|
||||||
(env->spr[SPR_BOOKE_TSR] & TSR_FIS
|
(env->spr[SPR_BOOKE_TSR] & TSR_FIS
|
||||||
&& env->spr[SPR_BOOKE_TCR] & TCR_FIE));
|
&& env->spr[SPR_BOOKE_TCR] & TCR_FIE));
|
||||||
}
|
}
|
||||||
|
@ -154,9 +156,10 @@ static void booke_update_fixed_timer(CPUPPCState *env,
|
||||||
static void booke_decr_cb(void *opaque)
|
static void booke_decr_cb(void *opaque)
|
||||||
{
|
{
|
||||||
CPUPPCState *env = opaque;
|
CPUPPCState *env = opaque;
|
||||||
|
PowerPCCPU *cpu = ppc_env_get_cpu(env);
|
||||||
|
|
||||||
env->spr[SPR_BOOKE_TSR] |= TSR_DIS;
|
env->spr[SPR_BOOKE_TSR] |= TSR_DIS;
|
||||||
booke_update_irq(env);
|
booke_update_irq(cpu);
|
||||||
|
|
||||||
if (env->spr[SPR_BOOKE_TCR] & TCR_ARE) {
|
if (env->spr[SPR_BOOKE_TCR] & TCR_ARE) {
|
||||||
/* Auto Reload */
|
/* Auto Reload */
|
||||||
|
@ -166,16 +169,18 @@ static void booke_decr_cb(void *opaque)
|
||||||
|
|
||||||
static void booke_fit_cb(void *opaque)
|
static void booke_fit_cb(void *opaque)
|
||||||
{
|
{
|
||||||
|
PowerPCCPU *cpu;
|
||||||
CPUPPCState *env;
|
CPUPPCState *env;
|
||||||
ppc_tb_t *tb_env;
|
ppc_tb_t *tb_env;
|
||||||
booke_timer_t *booke_timer;
|
booke_timer_t *booke_timer;
|
||||||
|
|
||||||
env = opaque;
|
env = opaque;
|
||||||
|
cpu = ppc_env_get_cpu(env);
|
||||||
tb_env = env->tb_env;
|
tb_env = env->tb_env;
|
||||||
booke_timer = tb_env->opaque;
|
booke_timer = tb_env->opaque;
|
||||||
env->spr[SPR_BOOKE_TSR] |= TSR_FIS;
|
env->spr[SPR_BOOKE_TSR] |= TSR_FIS;
|
||||||
|
|
||||||
booke_update_irq(env);
|
booke_update_irq(cpu);
|
||||||
|
|
||||||
booke_update_fixed_timer(env,
|
booke_update_fixed_timer(env,
|
||||||
booke_get_fit_target(env, tb_env),
|
booke_get_fit_target(env, tb_env),
|
||||||
|
@ -185,17 +190,19 @@ static void booke_fit_cb(void *opaque)
|
||||||
|
|
||||||
static void booke_wdt_cb(void *opaque)
|
static void booke_wdt_cb(void *opaque)
|
||||||
{
|
{
|
||||||
|
PowerPCCPU *cpu;
|
||||||
CPUPPCState *env;
|
CPUPPCState *env;
|
||||||
ppc_tb_t *tb_env;
|
ppc_tb_t *tb_env;
|
||||||
booke_timer_t *booke_timer;
|
booke_timer_t *booke_timer;
|
||||||
|
|
||||||
env = opaque;
|
env = opaque;
|
||||||
|
cpu = ppc_env_get_cpu(env);
|
||||||
tb_env = env->tb_env;
|
tb_env = env->tb_env;
|
||||||
booke_timer = tb_env->opaque;
|
booke_timer = tb_env->opaque;
|
||||||
|
|
||||||
/* TODO: There's lots of complicated stuff to do here */
|
/* TODO: There's lots of complicated stuff to do here */
|
||||||
|
|
||||||
booke_update_irq(env);
|
booke_update_irq(cpu);
|
||||||
|
|
||||||
booke_update_fixed_timer(env,
|
booke_update_fixed_timer(env,
|
||||||
booke_get_wdt_target(env, tb_env),
|
booke_get_wdt_target(env, tb_env),
|
||||||
|
@ -205,19 +212,22 @@ static void booke_wdt_cb(void *opaque)
|
||||||
|
|
||||||
void store_booke_tsr(CPUPPCState *env, target_ulong val)
|
void store_booke_tsr(CPUPPCState *env, target_ulong val)
|
||||||
{
|
{
|
||||||
|
PowerPCCPU *cpu = ppc_env_get_cpu(env);
|
||||||
|
|
||||||
env->spr[SPR_BOOKE_TSR] &= ~val;
|
env->spr[SPR_BOOKE_TSR] &= ~val;
|
||||||
booke_update_irq(env);
|
booke_update_irq(cpu);
|
||||||
}
|
}
|
||||||
|
|
||||||
void store_booke_tcr(CPUPPCState *env, target_ulong val)
|
void store_booke_tcr(CPUPPCState *env, target_ulong val)
|
||||||
{
|
{
|
||||||
|
PowerPCCPU *cpu = ppc_env_get_cpu(env);
|
||||||
ppc_tb_t *tb_env = env->tb_env;
|
ppc_tb_t *tb_env = env->tb_env;
|
||||||
booke_timer_t *booke_timer = tb_env->opaque;
|
booke_timer_t *booke_timer = tb_env->opaque;
|
||||||
|
|
||||||
tb_env = env->tb_env;
|
tb_env = env->tb_env;
|
||||||
env->spr[SPR_BOOKE_TCR] = val;
|
env->spr[SPR_BOOKE_TCR] = val;
|
||||||
|
|
||||||
booke_update_irq(env);
|
booke_update_irq(cpu);
|
||||||
|
|
||||||
booke_update_fixed_timer(env,
|
booke_update_fixed_timer(env,
|
||||||
booke_get_fit_target(env, tb_env),
|
booke_get_fit_target(env, tb_env),
|
||||||
|
|
Loading…
Reference in a new issue