target/arm: Remove CPSR_RESERVED
The only remaining use was in op_helper.c. Use PSTATE_SS directly, and move the commentary so that it is more obvious what is going on. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20200208125816.14954-10-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
parent
d203cabd1b
commit
70dae0d069
|
@ -1186,12 +1186,6 @@ void pmu_init(ARMCPU *cpu);
|
|||
#define CPSR_IT_2_7 (0xfc00U)
|
||||
#define CPSR_GE (0xfU << 16)
|
||||
#define CPSR_IL (1U << 20)
|
||||
/* Note that the RESERVED bits include bit 21, which is PSTATE_SS in
|
||||
* an AArch64 SPSR but RES0 in AArch32 SPSR and CPSR. In QEMU we use
|
||||
* env->uncached_cpsr bit 21 to store PSTATE.SS when executing in AArch32,
|
||||
* where it is live state but not accessible to the AArch32 code.
|
||||
*/
|
||||
#define CPSR_RESERVED (0x7U << 21)
|
||||
#define CPSR_J (1U << 24)
|
||||
#define CPSR_IT_0_1 (3U << 25)
|
||||
#define CPSR_Q (1U << 27)
|
||||
|
|
|
@ -387,7 +387,14 @@ void HELPER(exception_bkpt_insn)(CPUARMState *env, uint32_t syndrome)
|
|||
|
||||
uint32_t HELPER(cpsr_read)(CPUARMState *env)
|
||||
{
|
||||
return cpsr_read(env) & ~(CPSR_EXEC | CPSR_RESERVED);
|
||||
/*
|
||||
* We store the ARMv8 PSTATE.SS bit in env->uncached_cpsr.
|
||||
* This is convenient for populating SPSR_ELx, but must be
|
||||
* hidden from aarch32 mode, where it is not visible.
|
||||
*
|
||||
* TODO: ARMv8.4-DIT -- need to move SS somewhere else.
|
||||
*/
|
||||
return cpsr_read(env) & ~(CPSR_EXEC | PSTATE_SS);
|
||||
}
|
||||
|
||||
void HELPER(cpsr_write)(CPUARMState *env, uint32_t val, uint32_t mask)
|
||||
|
|
Loading…
Reference in a new issue