target/arm: Add support for FEAT_TLBIOS
ARMv8.4 adds the mandatory FEAT_TLBIOS. It provides TLBI maintenance instructions that extend to the Outer Shareable domain. Signed-off-by: Rebecca Cran <rebecca@nuviainc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210512182337.18563-3-rebecca@nuviainc.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
parent
84940ed825
commit
7113d61850
|
@ -4076,6 +4076,11 @@ static inline bool isar_feature_aa64_tlbirange(const ARMISARegisters *id)
|
||||||
return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TLB) == 2;
|
return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TLB) == 2;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
static inline bool isar_feature_aa64_tlbios(const ARMISARegisters *id)
|
||||||
|
{
|
||||||
|
return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TLB) != 0;
|
||||||
|
}
|
||||||
|
|
||||||
static inline bool isar_feature_aa64_sb(const ARMISARegisters *id)
|
static inline bool isar_feature_aa64_sb(const ARMISARegisters *id)
|
||||||
{
|
{
|
||||||
return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, SB) != 0;
|
return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, SB) != 0;
|
||||||
|
|
|
@ -7198,6 +7198,46 @@ static const ARMCPRegInfo tlbirange_reginfo[] = {
|
||||||
REGINFO_SENTINEL
|
REGINFO_SENTINEL
|
||||||
};
|
};
|
||||||
|
|
||||||
|
static const ARMCPRegInfo tlbios_reginfo[] = {
|
||||||
|
{ .name = "TLBI_VMALLE1OS", .state = ARM_CP_STATE_AA64,
|
||||||
|
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 1, .opc2 = 0,
|
||||||
|
.access = PL1_W, .type = ARM_CP_NO_RAW,
|
||||||
|
.writefn = tlbi_aa64_vmalle1is_write },
|
||||||
|
{ .name = "TLBI_ASIDE1OS", .state = ARM_CP_STATE_AA64,
|
||||||
|
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 1, .opc2 = 2,
|
||||||
|
.access = PL1_W, .type = ARM_CP_NO_RAW,
|
||||||
|
.writefn = tlbi_aa64_vmalle1is_write },
|
||||||
|
{ .name = "TLBI_ALLE2OS", .state = ARM_CP_STATE_AA64,
|
||||||
|
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 1, .opc2 = 0,
|
||||||
|
.access = PL2_W, .type = ARM_CP_NO_RAW,
|
||||||
|
.writefn = tlbi_aa64_alle2is_write },
|
||||||
|
{ .name = "TLBI_ALLE1OS", .state = ARM_CP_STATE_AA64,
|
||||||
|
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 1, .opc2 = 4,
|
||||||
|
.access = PL2_W, .type = ARM_CP_NO_RAW,
|
||||||
|
.writefn = tlbi_aa64_alle1is_write },
|
||||||
|
{ .name = "TLBI_VMALLS12E1OS", .state = ARM_CP_STATE_AA64,
|
||||||
|
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 1, .opc2 = 6,
|
||||||
|
.access = PL2_W, .type = ARM_CP_NO_RAW,
|
||||||
|
.writefn = tlbi_aa64_alle1is_write },
|
||||||
|
{ .name = "TLBI_IPAS2E1OS", .state = ARM_CP_STATE_AA64,
|
||||||
|
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 0,
|
||||||
|
.access = PL2_W, .type = ARM_CP_NOP },
|
||||||
|
{ .name = "TLBI_RIPAS2E1OS", .state = ARM_CP_STATE_AA64,
|
||||||
|
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 3,
|
||||||
|
.access = PL2_W, .type = ARM_CP_NOP },
|
||||||
|
{ .name = "TLBI_IPAS2LE1OS", .state = ARM_CP_STATE_AA64,
|
||||||
|
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 4,
|
||||||
|
.access = PL2_W, .type = ARM_CP_NOP },
|
||||||
|
{ .name = "TLBI_RIPAS2LE1OS", .state = ARM_CP_STATE_AA64,
|
||||||
|
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 7,
|
||||||
|
.access = PL2_W, .type = ARM_CP_NOP },
|
||||||
|
{ .name = "TLBI_ALLE3OS", .state = ARM_CP_STATE_AA64,
|
||||||
|
.opc0 = 1, .opc1 = 6, .crn = 8, .crm = 1, .opc2 = 0,
|
||||||
|
.access = PL3_W, .type = ARM_CP_NO_RAW,
|
||||||
|
.writefn = tlbi_aa64_alle3is_write },
|
||||||
|
REGINFO_SENTINEL
|
||||||
|
};
|
||||||
|
|
||||||
static uint64_t rndr_readfn(CPUARMState *env, const ARMCPRegInfo *ri)
|
static uint64_t rndr_readfn(CPUARMState *env, const ARMCPRegInfo *ri)
|
||||||
{
|
{
|
||||||
Error *err = NULL;
|
Error *err = NULL;
|
||||||
|
@ -8570,6 +8610,9 @@ void register_cp_regs_for_features(ARMCPU *cpu)
|
||||||
if (cpu_isar_feature(aa64_tlbirange, cpu)) {
|
if (cpu_isar_feature(aa64_tlbirange, cpu)) {
|
||||||
define_arm_cp_regs(cpu, tlbirange_reginfo);
|
define_arm_cp_regs(cpu, tlbirange_reginfo);
|
||||||
}
|
}
|
||||||
|
if (cpu_isar_feature(aa64_tlbios, cpu)) {
|
||||||
|
define_arm_cp_regs(cpu, tlbios_reginfo);
|
||||||
|
}
|
||||||
#ifndef CONFIG_USER_ONLY
|
#ifndef CONFIG_USER_ONLY
|
||||||
/* Data Cache clean instructions up to PoP */
|
/* Data Cache clean instructions up to PoP */
|
||||||
if (cpu_isar_feature(aa64_dcpop, cpu)) {
|
if (cpu_isar_feature(aa64_dcpop, cpu)) {
|
||||||
|
|
Loading…
Reference in a new issue