hw/intc/arm_gicv3: Fix APxR<n> register dispatching
There was a nasty flip in identifying which register group an access is
targeting. The issue caused spuriously raised priorities of the guest
when handing CPUs over in the Jailhouse hypervisor.
Cc: qemu-stable@nongnu.org
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Message-id: 28b927d3-da58-bce4-cc13-bfec7f9b1cb9@siemens.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
(cherry picked from commit 887aae10f6
)
Signed-off-by: Michael Roth <mdroth@linux.vnet.ibm.com>
stable-2.11
parent
2e70085eb7
commit
7128bcb221
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@ -431,7 +431,7 @@ static uint64_t icv_ap_read(CPUARMState *env, const ARMCPRegInfo *ri)
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{
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GICv3CPUState *cs = icc_cs_from_env(env);
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int regno = ri->opc2 & 3;
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int grp = ri->crm & 1 ? GICV3_G0 : GICV3_G1NS;
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int grp = (ri->crm & 1) ? GICV3_G1NS : GICV3_G0;
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uint64_t value = cs->ich_apr[grp][regno];
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trace_gicv3_icv_ap_read(ri->crm & 1, regno, gicv3_redist_affid(cs), value);
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@ -443,7 +443,7 @@ static void icv_ap_write(CPUARMState *env, const ARMCPRegInfo *ri,
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{
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GICv3CPUState *cs = icc_cs_from_env(env);
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int regno = ri->opc2 & 3;
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int grp = ri->crm & 1 ? GICV3_G0 : GICV3_G1NS;
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int grp = (ri->crm & 1) ? GICV3_G1NS : GICV3_G0;
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trace_gicv3_icv_ap_write(ri->crm & 1, regno, gicv3_redist_affid(cs), value);
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@ -1465,7 +1465,7 @@ static uint64_t icc_ap_read(CPUARMState *env, const ARMCPRegInfo *ri)
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uint64_t value;
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int regno = ri->opc2 & 3;
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int grp = ri->crm & 1 ? GICV3_G0 : GICV3_G1;
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int grp = (ri->crm & 1) ? GICV3_G1 : GICV3_G0;
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if (icv_access(env, grp == GICV3_G0 ? HCR_FMO : HCR_IMO)) {
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return icv_ap_read(env, ri);
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@ -1487,7 +1487,7 @@ static void icc_ap_write(CPUARMState *env, const ARMCPRegInfo *ri,
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GICv3CPUState *cs = icc_cs_from_env(env);
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int regno = ri->opc2 & 3;
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int grp = ri->crm & 1 ? GICV3_G0 : GICV3_G1;
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int grp = (ri->crm & 1) ? GICV3_G1 : GICV3_G0;
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if (icv_access(env, grp == GICV3_G0 ? HCR_FMO : HCR_IMO)) {
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icv_ap_write(env, ri, value);
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@ -2296,7 +2296,7 @@ static uint64_t ich_ap_read(CPUARMState *env, const ARMCPRegInfo *ri)
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{
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GICv3CPUState *cs = icc_cs_from_env(env);
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int regno = ri->opc2 & 3;
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int grp = ri->crm & 1 ? GICV3_G0 : GICV3_G1NS;
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int grp = (ri->crm & 1) ? GICV3_G1NS : GICV3_G0;
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uint64_t value;
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value = cs->ich_apr[grp][regno];
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@ -2309,7 +2309,7 @@ static void ich_ap_write(CPUARMState *env, const ARMCPRegInfo *ri,
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{
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GICv3CPUState *cs = icc_cs_from_env(env);
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int regno = ri->opc2 & 3;
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int grp = ri->crm & 1 ? GICV3_G0 : GICV3_G1NS;
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int grp = (ri->crm & 1) ? GICV3_G1NS : GICV3_G0;
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trace_gicv3_ich_ap_write(ri->crm & 1, regno, gicv3_redist_affid(cs), value);
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