openpic: Memory API conversion for mpic
This patch converts mpic to the new memory API (through old mmio). Signed-off-by: Fabien Chouteau <chouteau@adacore.com> Signed-off-by: Avi Kivity <avi@redhat.com>
This commit is contained in:
Fabien Chouteau
Avi Kivity
parent
5a95b51dd8
commit
71cf9e6242
209
hw/openpic.c
209
hw/openpic.c
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@ -206,6 +206,10 @@ typedef struct IRQ_dst_t {
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typedef struct openpic_t {
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PCIDevice pci_dev;
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MemoryRegion mem;
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/* Sub-regions */
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MemoryRegion sub_io_mem[7];
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/* Global registers */
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uint32_t frep; /* Feature reporting register */
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uint32_t glbc; /* Global configuration register */
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@ -1537,107 +1541,122 @@ static uint32_t mpic_src_msi_read (void *opaque, target_phys_addr_t addr)
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return retval;
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}
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static CPUWriteMemoryFunc * const mpic_glb_write[] = {
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&openpic_buggy_write,
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&openpic_buggy_write,
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&openpic_gbl_write,
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static const MemoryRegionOps mpic_glb_ops = {
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.old_mmio = {
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.write = { openpic_buggy_write,
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openpic_buggy_write,
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openpic_gbl_write,
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},
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.read = { openpic_buggy_read,
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openpic_buggy_read,
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openpic_gbl_read,
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},
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},
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.endianness = DEVICE_BIG_ENDIAN,
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};
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static CPUReadMemoryFunc * const mpic_glb_read[] = {
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&openpic_buggy_read,
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&openpic_buggy_read,
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&openpic_gbl_read,
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static const MemoryRegionOps mpic_tmr_ops = {
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.old_mmio = {
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.write = { openpic_buggy_write,
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openpic_buggy_write,
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mpic_timer_write,
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},
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.read = { openpic_buggy_read,
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openpic_buggy_read,
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mpic_timer_read,
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},
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},
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.endianness = DEVICE_BIG_ENDIAN,
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};
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static CPUWriteMemoryFunc * const mpic_tmr_write[] = {
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&openpic_buggy_write,
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&openpic_buggy_write,
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&mpic_timer_write,
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static const MemoryRegionOps mpic_cpu_ops = {
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.old_mmio = {
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.write = { openpic_buggy_write,
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openpic_buggy_write,
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openpic_cpu_write,
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},
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.read = { openpic_buggy_read,
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openpic_buggy_read,
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openpic_cpu_read,
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},
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},
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.endianness = DEVICE_BIG_ENDIAN,
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};
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static CPUReadMemoryFunc * const mpic_tmr_read[] = {
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&openpic_buggy_read,
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&openpic_buggy_read,
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&mpic_timer_read,
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static const MemoryRegionOps mpic_ext_ops = {
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.old_mmio = {
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.write = { openpic_buggy_write,
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openpic_buggy_write,
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mpic_src_ext_write,
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},
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.read = { openpic_buggy_read,
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openpic_buggy_read,
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mpic_src_ext_read,
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},
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},
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.endianness = DEVICE_BIG_ENDIAN,
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};
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static CPUWriteMemoryFunc * const mpic_cpu_write[] = {
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&openpic_buggy_write,
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&openpic_buggy_write,
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&openpic_cpu_write,
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static const MemoryRegionOps mpic_int_ops = {
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.old_mmio = {
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.write = { openpic_buggy_write,
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openpic_buggy_write,
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mpic_src_int_write,
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},
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.read = { openpic_buggy_read,
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openpic_buggy_read,
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mpic_src_int_read,
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},
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},
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.endianness = DEVICE_BIG_ENDIAN,
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};
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static CPUReadMemoryFunc * const mpic_cpu_read[] = {
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&openpic_buggy_read,
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&openpic_buggy_read,
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&openpic_cpu_read,
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static const MemoryRegionOps mpic_msg_ops = {
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.old_mmio = {
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.write = { openpic_buggy_write,
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openpic_buggy_write,
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mpic_src_msg_write,
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},
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.read = { openpic_buggy_read,
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openpic_buggy_read,
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mpic_src_msg_read,
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},
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},
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.endianness = DEVICE_BIG_ENDIAN,
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};
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static CPUWriteMemoryFunc * const mpic_ext_write[] = {
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&openpic_buggy_write,
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&openpic_buggy_write,
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&mpic_src_ext_write,
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static const MemoryRegionOps mpic_msi_ops = {
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.old_mmio = {
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.write = { openpic_buggy_write,
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openpic_buggy_write,
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mpic_src_msi_write,
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},
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.read = { openpic_buggy_read,
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openpic_buggy_read,
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mpic_src_msi_read,
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},
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},
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.endianness = DEVICE_BIG_ENDIAN,
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};
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static CPUReadMemoryFunc * const mpic_ext_read[] = {
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&openpic_buggy_read,
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&openpic_buggy_read,
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&mpic_src_ext_read,
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};
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static CPUWriteMemoryFunc * const mpic_int_write[] = {
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&openpic_buggy_write,
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&openpic_buggy_write,
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&mpic_src_int_write,
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};
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static CPUReadMemoryFunc * const mpic_int_read[] = {
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&openpic_buggy_read,
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&openpic_buggy_read,
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&mpic_src_int_read,
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};
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static CPUWriteMemoryFunc * const mpic_msg_write[] = {
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&openpic_buggy_write,
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&openpic_buggy_write,
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&mpic_src_msg_write,
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};
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static CPUReadMemoryFunc * const mpic_msg_read[] = {
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&openpic_buggy_read,
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&openpic_buggy_read,
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&mpic_src_msg_read,
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};
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static CPUWriteMemoryFunc * const mpic_msi_write[] = {
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&openpic_buggy_write,
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&openpic_buggy_write,
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&mpic_src_msi_write,
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};
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static CPUReadMemoryFunc * const mpic_msi_read[] = {
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&openpic_buggy_read,
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&openpic_buggy_read,
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&mpic_src_msi_read,
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};
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qemu_irq *mpic_init (target_phys_addr_t base, int nb_cpus,
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qemu_irq **irqs, qemu_irq irq_out)
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qemu_irq *mpic_init (MemoryRegion *address_space, target_phys_addr_t base,
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int nb_cpus, qemu_irq **irqs, qemu_irq irq_out)
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{
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openpic_t *mpp;
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int i;
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openpic_t *mpp;
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int i;
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struct {
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CPUReadMemoryFunc * const *read;
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CPUWriteMemoryFunc * const *write;
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target_phys_addr_t start_addr;
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ram_addr_t size;
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const char *name;
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MemoryRegionOps const *ops;
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target_phys_addr_t start_addr;
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ram_addr_t size;
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} const list[] = {
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{mpic_glb_read, mpic_glb_write, MPIC_GLB_REG_START, MPIC_GLB_REG_SIZE},
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{mpic_tmr_read, mpic_tmr_write, MPIC_TMR_REG_START, MPIC_TMR_REG_SIZE},
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{mpic_ext_read, mpic_ext_write, MPIC_EXT_REG_START, MPIC_EXT_REG_SIZE},
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{mpic_int_read, mpic_int_write, MPIC_INT_REG_START, MPIC_INT_REG_SIZE},
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{mpic_msg_read, mpic_msg_write, MPIC_MSG_REG_START, MPIC_MSG_REG_SIZE},
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{mpic_msi_read, mpic_msi_write, MPIC_MSI_REG_START, MPIC_MSI_REG_SIZE},
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{mpic_cpu_read, mpic_cpu_write, MPIC_CPU_REG_START, MPIC_CPU_REG_SIZE},
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{"glb", &mpic_glb_ops, MPIC_GLB_REG_START, MPIC_GLB_REG_SIZE},
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{"tmr", &mpic_tmr_ops, MPIC_TMR_REG_START, MPIC_TMR_REG_SIZE},
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{"ext", &mpic_ext_ops, MPIC_EXT_REG_START, MPIC_EXT_REG_SIZE},
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{"int", &mpic_int_ops, MPIC_INT_REG_START, MPIC_INT_REG_SIZE},
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{"msg", &mpic_msg_ops, MPIC_MSG_REG_START, MPIC_MSG_REG_SIZE},
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{"msi", &mpic_msi_ops, MPIC_MSI_REG_START, MPIC_MSI_REG_SIZE},
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{"cpu", &mpic_cpu_ops, MPIC_CPU_REG_START, MPIC_CPU_REG_SIZE},
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};
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/* XXX: for now, only one CPU is supported */
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@ -1646,16 +1665,16 @@ qemu_irq *mpic_init (target_phys_addr_t base, int nb_cpus,
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mpp = g_malloc0(sizeof(openpic_t));
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for (i = 0; i < sizeof(list)/sizeof(list[0]); i++) {
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int mem_index;
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memory_region_init(&mpp->mem, "mpic", 0x40000);
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memory_region_add_subregion(address_space, base, &mpp->mem);
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mem_index = cpu_register_io_memory(list[i].read, list[i].write, mpp,
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DEVICE_BIG_ENDIAN);
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if (mem_index < 0) {
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goto free;
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}
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cpu_register_physical_memory(base + list[i].start_addr,
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list[i].size, mem_index);
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for (i = 0; i < sizeof(list)/sizeof(list[0]); i++) {
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memory_region_init_io(&mpp->sub_io_mem[i], list[i].ops, mpp,
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list[i].name, list[i].size);
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memory_region_add_subregion(&mpp->mem, list[i].start_addr,
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&mpp->sub_io_mem[i]);
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}
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mpp->nb_cpus = nb_cpus;
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@ -1674,8 +1693,4 @@ qemu_irq *mpic_init (target_phys_addr_t base, int nb_cpus,
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qemu_register_reset(mpic_reset, mpp);
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return qemu_allocate_irqs(openpic_set_irq, mpp, mpp->max_irq);
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free:
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g_free(mpp);
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return NULL;
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}
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@ -13,6 +13,6 @@ enum {
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qemu_irq *openpic_init (PCIBus *bus, MemoryRegion **pmem, int nb_cpus,
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qemu_irq **irqs, qemu_irq irq_out);
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qemu_irq *mpic_init (target_phys_addr_t base, int nb_cpus,
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qemu_irq **irqs, qemu_irq irq_out);
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qemu_irq *mpic_init (MemoryRegion *address_space, target_phys_addr_t base,
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int nb_cpus, qemu_irq **irqs, qemu_irq irq_out);
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#endif /* __OPENPIC_H__ */
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@ -272,7 +272,7 @@ static void mpc8544ds_init(ram_addr_t ram_size,
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irqs = g_malloc0(sizeof(qemu_irq) * OPENPIC_OUTPUT_NB);
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irqs[OPENPIC_OUTPUT_INT] = ((qemu_irq *)env->irq_inputs)[PPCE500_INPUT_INT];
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irqs[OPENPIC_OUTPUT_CINT] = ((qemu_irq *)env->irq_inputs)[PPCE500_INPUT_CINT];
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mpic = mpic_init(MPC8544_MPIC_REGS_BASE, 1, &irqs, NULL);
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mpic = mpic_init(address_space_mem, MPC8544_MPIC_REGS_BASE, 1, &irqs, NULL);
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/* Serial */
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if (serial_hds[0]) {
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