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target/mips: Allow Loongson 3A1000 to use up to 48-bit VAddr

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Per the manual '龙芯 GS264 处理器核用户手册' v1.0, chapter
1.1.5 SEGBITS: the 3A1000 (based on GS464 core) implements
48 virtual address bits in each 64-bit segment, not 40.

Fixes: af868995e1 ("target/mips: Add Loongson-3 CPU definition")
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Huacai Chen <chenhuacai@loongson.cn>
Message-Id: <20210813110149.1432692-3-f4bug@amsat.org>
This commit is contained in:
Philippe Mathieu-Daudé 2021-08-13 12:36:46 +02:00
parent 98d207cf9c
commit 71ed30b7d4
1 changed files with 1 additions and 1 deletions
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target/mips/cpu-defs.c.inc
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@ -828,7 +828,7 @@ const mips_def_t mips_defs[] =
(0x1 << FCR0_D) | (0x1 << FCR0_S),
.CP1_fcr31 = 0,
.CP1_fcr31_rw_bitmask = 0xFF83FFFF,
.SEGBITS = 42,
.SEGBITS = 48,
.PABITS = 48,
.insn_flags = CPU_MIPS64R2 | INSN_LOONGSON3A |
ASE_LMMI | ASE_LEXT,