m68k pull request 20210526
implement m68k "any instruction" trace mode -----BEGIN PGP SIGNATURE----- iQJGBAABCAAwFiEEzS913cjjpNwuT1Fz8ww4vT8vvjwFAmCuqAoSHGxhdXJlbnRA dml2aWVyLmV1AAoJEPMMOL0/L748pisQALGWkrw9vYqcinTGeR0gRIbqexZCCZ9S sTSp+2BJ+uHletEXg0jjl/+3Rh+ILWE9EFT3CcXnWp0vFCHaxWZjW2Ez2tPwMBuF A0S2VCUIrvdu7JFb8J8q5NavVlcsd/peP22VM4XuOwHwc4h7nA5ihUexfZMmppVz CtiiHXmTa5VBNg4Ae4M3UnTgQlYaftnsVblG0FVZqs8MCb2e4WUd52ILEyu1a7/p wHna5qICqEf69HWMGXSab3x2YZV+SKD0A8EdCmJIme//YcJKqFJ4YouwG5WyhKR9 uYbnTRXbihLXWvC3M7cwPsiIimK/AMlNbufzmhWDOGEB5EwDD0LDfPhx53TM8KMv YquHzj+DtPx3alTeEtBaLTt5ImOPj7s7pwCbM3CF+ERZQ9LJ6mEnxkkgpUNTeUIz TgT4M3vLl1VglpMCUZojUaQHvA/M1y6pHdNEuXt0RMjXWVhjB7RLn+TcEwVt8YCA pf2U9PnbZb450OH8nHNPK/qN1z6G67zaPa99cwem1WXUWCRYVKoRcOPfd1m+gmmT ANWSdFDkBlBRfp1dZ4o0qWZ1odf96I8oZFhWKzUNcMFdlxiGiAjceWU0VJNZ+mPJ Pt+VYPsg0KUSQEWc0aOLgPaQHrPXjPQI+dAkdShOdbsiKbgbq2NV0ej8YVqiczu6 +Kc+mGybCPf/ =WElK -----END PGP SIGNATURE----- Merge remote-tracking branch 'remotes/vivier/tags/m68k-for-6.1-pull-request' into staging m68k pull request 20210526 implement m68k "any instruction" trace mode # gpg: Signature made Wed 26 May 2021 20:56:58 BST # gpg: using RSA key CD2F75DDC8E3A4DC2E4F5173F30C38BD3F2FBE3C # gpg: issuer "laurent@vivier.eu" # gpg: Good signature from "Laurent Vivier <lvivier@redhat.com>" [full] # gpg: aka "Laurent Vivier <laurent@vivier.eu>" [full] # gpg: aka "Laurent Vivier (Red Hat) <lvivier@redhat.com>" [full] # Primary key fingerprint: CD2F 75DD C8E3 A4DC 2E4F 5173 F30C 38BD 3F2F BE3C * remotes/vivier/tags/m68k-for-6.1-pull-request: target/m68k: implement m68k "any instruction" trace mode target/m68k: introduce gen_singlestep_exception() function target/m68k: call gen_raise_exception() directly if single-stepping in gen_jmp_tb() target/m68k: introduce is_singlestepping() function Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
commit
7258034ab4
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@ -230,6 +230,9 @@ typedef enum {
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#define SR_T_SHIFT 14
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#define SR_T_SHIFT 14
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#define SR_T 0xc000
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#define SR_T 0xc000
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#define M68K_SR_TRACE(sr) ((sr & SR_T) >> SR_T_SHIFT)
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#define M68K_SR_TRACE_ANY_INS 0x2
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#define M68K_SSP 0
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#define M68K_SSP 0
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#define M68K_USP 1
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#define M68K_USP 1
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#define M68K_ISP 2
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#define M68K_ISP 2
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@ -590,6 +593,8 @@ typedef M68kCPU ArchCPU;
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#define TB_FLAGS_SFC_S (1 << TB_FLAGS_SFC_S_BIT)
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#define TB_FLAGS_SFC_S (1 << TB_FLAGS_SFC_S_BIT)
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#define TB_FLAGS_DFC_S_BIT 15
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#define TB_FLAGS_DFC_S_BIT 15
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#define TB_FLAGS_DFC_S (1 << TB_FLAGS_DFC_S_BIT)
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#define TB_FLAGS_DFC_S (1 << TB_FLAGS_DFC_S_BIT)
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#define TB_FLAGS_TRACE 16
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#define TB_FLAGS_TRACE_BIT (1 << TB_FLAGS_TRACE)
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static inline void cpu_get_tb_cpu_state(CPUM68KState *env, target_ulong *pc,
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static inline void cpu_get_tb_cpu_state(CPUM68KState *env, target_ulong *pc,
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target_ulong *cs_base, uint32_t *flags)
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target_ulong *cs_base, uint32_t *flags)
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@ -602,6 +607,9 @@ static inline void cpu_get_tb_cpu_state(CPUM68KState *env, target_ulong *pc,
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*flags |= (env->sfc << (TB_FLAGS_SFC_S_BIT - 2)) & TB_FLAGS_SFC_S;
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*flags |= (env->sfc << (TB_FLAGS_SFC_S_BIT - 2)) & TB_FLAGS_SFC_S;
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*flags |= (env->dfc << (TB_FLAGS_DFC_S_BIT - 2)) & TB_FLAGS_DFC_S;
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*flags |= (env->dfc << (TB_FLAGS_DFC_S_BIT - 2)) & TB_FLAGS_DFC_S;
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}
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}
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if (M68K_SR_TRACE(env->sr) == M68K_SR_TRACE_ANY_INS) {
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*flags |= TB_FLAGS_TRACE;
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}
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}
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}
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void dump_mmu(CPUM68KState *env);
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void dump_mmu(CPUM68KState *env);
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@ -124,6 +124,7 @@ typedef struct DisasContext {
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#define MAX_TO_RELEASE 8
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#define MAX_TO_RELEASE 8
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int release_count;
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int release_count;
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TCGv release[MAX_TO_RELEASE];
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TCGv release[MAX_TO_RELEASE];
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bool ss_active;
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} DisasContext;
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} DisasContext;
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static void init_release_array(DisasContext *s)
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static void init_release_array(DisasContext *s)
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@ -194,6 +195,18 @@ static void do_writebacks(DisasContext *s)
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}
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}
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}
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}
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static bool is_singlestepping(DisasContext *s)
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{
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/*
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* Return true if we are singlestepping either because of
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* architectural singlestep or QEMU gdbstub singlestep. This does
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* not include the command line '-singlestep' mode which is rather
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* misnamed as it only means "one instruction per TB" and doesn't
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* affect the code we generate.
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*/
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return s->base.singlestep_enabled || s->ss_active;
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}
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/* is_jmp field values */
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/* is_jmp field values */
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#define DISAS_JUMP DISAS_TARGET_0 /* only pc was modified dynamically */
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#define DISAS_JUMP DISAS_TARGET_0 /* only pc was modified dynamically */
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#define DISAS_EXIT DISAS_TARGET_1 /* cpu state was modified dynamically */
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#define DISAS_EXIT DISAS_TARGET_1 /* cpu state was modified dynamically */
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@ -308,6 +321,20 @@ static void gen_exception(DisasContext *s, uint32_t dest, int nr)
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s->base.is_jmp = DISAS_NORETURN;
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s->base.is_jmp = DISAS_NORETURN;
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}
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}
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static void gen_singlestep_exception(DisasContext *s)
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{
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/*
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* Generate the right kind of exception for singlestep, which is
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* either the architectural singlestep or EXCP_DEBUG for QEMU's
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* gdb singlestepping.
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*/
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if (s->ss_active) {
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gen_raise_exception(EXCP_TRACE);
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} else {
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gen_raise_exception(EXCP_DEBUG);
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}
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}
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static inline void gen_addr_fault(DisasContext *s)
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static inline void gen_addr_fault(DisasContext *s)
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{
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{
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gen_exception(s, s->base.pc_next, EXCP_ADDRESS);
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gen_exception(s, s->base.pc_next, EXCP_ADDRESS);
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@ -1506,8 +1533,10 @@ static inline bool use_goto_tb(DisasContext *s, uint32_t dest)
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/* Generate a jump to an immediate address. */
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/* Generate a jump to an immediate address. */
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static void gen_jmp_tb(DisasContext *s, int n, uint32_t dest)
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static void gen_jmp_tb(DisasContext *s, int n, uint32_t dest)
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{
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{
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if (unlikely(s->base.singlestep_enabled)) {
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if (unlikely(is_singlestepping(s))) {
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gen_exception(s, dest, EXCP_DEBUG);
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update_cc_op(s);
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tcg_gen_movi_i32(QREG_PC, dest);
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gen_singlestep_exception(s);
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} else if (use_goto_tb(s, dest)) {
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} else if (use_goto_tb(s, dest)) {
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tcg_gen_goto_tb(n);
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tcg_gen_goto_tb(n);
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tcg_gen_movi_i32(QREG_PC, dest);
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tcg_gen_movi_i32(QREG_PC, dest);
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@ -6172,6 +6201,12 @@ static void m68k_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cpu)
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dc->done_mac = 0;
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dc->done_mac = 0;
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dc->writeback_mask = 0;
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dc->writeback_mask = 0;
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init_release_array(dc);
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init_release_array(dc);
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dc->ss_active = (M68K_SR_TRACE(env->sr) == M68K_SR_TRACE_ANY_INS);
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/* If architectural single step active, limit to 1 */
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if (is_singlestepping(dc)) {
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dc->base.max_insns = 1;
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}
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}
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}
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static void m68k_tr_tb_start(DisasContextBase *dcbase, CPUState *cpu)
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static void m68k_tr_tb_start(DisasContextBase *dcbase, CPUState *cpu)
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@ -6245,17 +6280,17 @@ static void m68k_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
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break;
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break;
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case DISAS_TOO_MANY:
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case DISAS_TOO_MANY:
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update_cc_op(dc);
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update_cc_op(dc);
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if (dc->base.singlestep_enabled) {
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if (is_singlestepping(dc)) {
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tcg_gen_movi_i32(QREG_PC, dc->pc);
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tcg_gen_movi_i32(QREG_PC, dc->pc);
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gen_raise_exception(EXCP_DEBUG);
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gen_singlestep_exception(dc);
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} else {
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} else {
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gen_jmp_tb(dc, 0, dc->pc);
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gen_jmp_tb(dc, 0, dc->pc);
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}
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}
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break;
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break;
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case DISAS_JUMP:
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case DISAS_JUMP:
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/* We updated CC_OP and PC in gen_jmp/gen_jmp_im. */
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/* We updated CC_OP and PC in gen_jmp/gen_jmp_im. */
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if (dc->base.singlestep_enabled) {
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if (is_singlestepping(dc)) {
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gen_raise_exception(EXCP_DEBUG);
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gen_singlestep_exception(dc);
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} else {
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} else {
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tcg_gen_lookup_and_goto_ptr();
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tcg_gen_lookup_and_goto_ptr();
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}
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}
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@ -6265,8 +6300,8 @@ static void m68k_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
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* We updated CC_OP and PC in gen_exit_tb, but also modified
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* We updated CC_OP and PC in gen_exit_tb, but also modified
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* other state that may require returning to the main loop.
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* other state that may require returning to the main loop.
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*/
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*/
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if (dc->base.singlestep_enabled) {
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if (is_singlestepping(dc)) {
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gen_raise_exception(EXCP_DEBUG);
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gen_singlestep_exception(dc);
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} else {
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} else {
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tcg_gen_exit_tb(NULL, 0);
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tcg_gen_exit_tb(NULL, 0);
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}
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}
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